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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml21 - one or more IRS (Interrupt Routing Service)
78 "^irs@[0-9a-f]+$":
81 GICv5 has one or more Interrupt Routing Services (IRS) that are
88 const: arm,gic-v5-irs
93 - description: IRS config frames
94 - description: IRS setlpi frames
117 Present if the GIC IRS permits programming shareability and
123 CPUs managed by the IRS.
137 ITS is connected to an IRS.
236 irs@2f1a0000 {
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/linux/drivers/irqchip/
H A Dirq-gic-v5-irs.c6 #define pr_fmt(fmt) "GICv5 IRS: " fmt
240 * Make sure we invalidate the cache line pulled before the IRS in gicv5_irs_iste_alloc()
521 pr_err("No IRS associated with CPU %u\n", cpuid); in gicv5_irs_register_cpu()
558 * A non-coherent IRS implies that some cache levels cannot be in gicv5_irs_init_bases()
602 * record IRS<->CPU topology information. in gicv5_irs_of_init_affinity()
640 pr_warn("CPU %d iaffid 0x%x exceeds IRS iaffid bits\n", in gicv5_irs_of_init_affinity()
648 /* We also know that the CPU is connected to this IRS */ in gicv5_irs_of_init_affinity()
703 pr_err("%pOF: unable to map GICv5 IRS registers\n", node); in gicv5_irs_init()
741 * Do the global setting only on the first IRS. in gicv5_irs_init()
818 if (!of_device_is_compatible(np, "arm,gic-v5-irs")) in gicv5_irs_of_probe()
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/linux/sound/hda/core/
H A Dcontroller.c145 if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) { in snd_hdac_bus_wait_for_pio_response()
153 dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n", in snd_hdac_bus_wait_for_pio_response()
154 snd_hdac_chip_readw(bus, IRS)); in snd_hdac_bus_wait_for_pio_response()
177 if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) { in snd_hdac_bus_send_cmd_pio()
179 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID); in snd_hdac_bus_send_cmd_pio()
182 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY); in snd_hdac_bus_send_cmd_pio()
189 dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n", in snd_hdac_bus_send_cmd_pio()
190 snd_hdac_chip_readw(bus, IRS), val); in snd_hdac_bus_send_cmd_pio()
/linux/sound/hda/common/
H A Dcontroller.c843 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
851 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", in azx_single_wait_for_response()
852 azx_readw(chip, IRS)); in azx_single_wait_for_response()
867 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { in azx_single_send_cmd()
869 azx_writew(chip, IRS, azx_readw(chip, IRS) | in azx_single_send_cmd()
872 azx_writew(chip, IRS, azx_readw(chip, IRS) | in azx_single_send_cmd()
880 "send_cmd timeout: IRS=0x%x, val=0x%x\n", in azx_single_send_cmd()
881 azx_readw(chip, IRS), va in azx_single_send_cmd()
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/linux/drivers/iio/proximity/
H A DKconfig59 tristate "Murata IRS-D200 PIR sensor"
65 Say Y here to build a driver for the Murata IRS-D200 PIR sensor.
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dmurata,irsd200.yaml7 title: Murata IRS-D200 PIR sensor
/linux/drivers/media/pci/ddbridge/
H A Dddbridge-i2c.c46 dev_err(dev->dev, "DDBridge IRS %08x\n", istat); in ddb_i2c_cmd()
52 dev_err(dev->dev, "DDBridge link %u IRS %08x\n", in ddb_i2c_cmd()
/linux/arch/s390/kernel/
H A Debcdic.c29 /* ->IGS ->IRS ->IUS */
101 /* 0x18 CAN EM -UBS -CU1 -IFS -IGS -IRS -ITB
178 /* ->IGS ->IRS ->IUS */
250 /* 0x18 CAN EM -UBS -CU1 -IFS -IGS -IRS -ITB
/linux/include/linux/irqchip/
H A Darm-gic-v5.h44 * IRS registers and tables structures
/linux/drivers/infiniband/hw/cxgb4/
H A Dt4fw_ri_api.h779 __be32 irs; member
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c9237 * 1. Sync IRS for default SB in bnx2x_func_wait_started()