Lines Matching full:irs
6 #define pr_fmt(fmt) "GICv5 IRS: " fmt
240 * Make sure we invalidate the cache line pulled before the IRS in gicv5_irs_iste_alloc()
521 pr_err("No IRS associated with CPU %u\n", cpuid); in gicv5_irs_register_cpu()
558 * A non-coherent IRS implies that some cache levels cannot be in gicv5_irs_init_bases()
602 * record IRS<->CPU topology information. in gicv5_irs_of_init_affinity()
640 pr_warn("CPU %d iaffid 0x%x exceeds IRS iaffid bits\n", in gicv5_irs_of_init_affinity()
648 /* We also know that the CPU is connected to this IRS */ in gicv5_irs_of_init_affinity()
703 pr_err("%pOF: unable to map GICv5 IRS registers\n", node); in gicv5_irs_init()
741 * Do the global setting only on the first IRS. in gicv5_irs_init()
818 if (!of_device_is_compatible(np, "arm,gic-v5-irs")) in gicv5_irs_of_probe()
823 pr_err("Failed to init IRS %s\n", np->full_name); in gicv5_irs_of_probe()