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/linux/drivers/net/ethernet/cavium/liquidio/
H A Drequest_manager.c51 struct octeon_instr_queue *iq; in octeon_init_instr_queue() local
73 iq = oct->instr_queue[iq_no]; in octeon_init_instr_queue()
75 iq->oct_dev = oct; in octeon_init_instr_queue()
77 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma); in octeon_init_instr_queue()
78 if (!iq->base_addr) { in octeon_init_instr_queue()
84 iq->max_count = num_descs; in octeon_init_instr_queue()
89 iq->request_list = vzalloc_node(array_size(num_descs, sizeof(*iq->request_list)), in octeon_init_instr_queue()
91 if (!iq->request_list) in octeon_init_instr_queue()
92 iq->request_list = vzalloc(array_size(num_descs, sizeof(*iq->request_list))); in octeon_init_instr_queue()
93 if (!iq->request_list) { in octeon_init_instr_queue()
[all …]
H A Dcn23xx_vf_device.c58 /* set RST bit to 1. This bit applies to both IQ and OQ */ in cn23xx_vf_reset_io_queues()
104 struct octeon_instr_queue *iq; in cn23xx_vf_setup_global_input_regs() local
116 iq = oct->instr_queue[q_no]; in cn23xx_vf_setup_global_input_regs()
118 if (iq) in cn23xx_vf_setup_global_input_regs()
119 inst_cnt_reg = iq->inst_cnt_reg; in cn23xx_vf_setup_global_input_regs()
214 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in cn23xx_setup_vf_iq_regs() local
219 iq->base_addr_dma); in cn23xx_setup_vf_iq_regs()
220 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count); in cn23xx_setup_vf_iq_regs()
225 iq->doorbell_reg = in cn23xx_setup_vf_iq_regs()
227 iq->inst_cnt_reg = in cn23xx_setup_vf_iq_regs()
[all …]
H A Dcn66xx_device.c266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn6xxx_setup_iq_regs() local
272 iq->base_addr_dma); in lio_cn6xxx_setup_iq_regs()
273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn6xxx_setup_iq_regs()
278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); in lio_cn6xxx_setup_iq_regs()
279 iq->inst_cnt_reg = oct->mmio[0].hw_addr in lio_cn6xxx_setup_iq_regs()
282 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
287 iq->reset_instr_cnt = readl(iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
339 mask |= oct->io_qmask.iq; in lio_cn6xxx_enable_io_queues()
357 mask ^= oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
361 mask = (u32)oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
[all …]
H A Docteon_config.h42 /* CN6xxx IQ configuration macros */
64 /* CN23xx IQ configuration macros */
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
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H A Dcn23xx_pf_device.c191 /* set RST bit to 1. This bit applies to both IQ and OQ */ in cn23xx_reset_io_queues()
234 struct octeon_instr_queue *iq; in cn23xx_pf_setup_global_input_regs() local
277 iq = oct->instr_queue[q_no]; in cn23xx_pf_setup_global_input_regs()
278 if (iq) in cn23xx_pf_setup_global_input_regs()
279 inst_cnt_reg = iq->inst_cnt_reg; in cn23xx_pf_setup_global_input_regs()
420 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in cn23xx_setup_iq_regs() local
427 iq->base_addr_dma); in cn23xx_setup_iq_regs()
428 octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count); in cn23xx_setup_iq_regs()
433 iq->doorbell_reg = in cn23xx_setup_iq_regs()
435 iq->inst_cnt_reg = in cn23xx_setup_iq_regs()
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H A Dcn23xx_vf_regs.h70 #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \ argument
71 (CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
73 #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \ argument
74 (CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
76 #define CN23XX_VF_SLI_IQ_SIZE(iq) \ argument
77 (CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET))
79 #define CN23XX_VF_SLI_IQ_DOORBELL(iq) \ argument
80 (CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET))
82 #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \ argument
83 (CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
H A Dcn66xx_regs.h143 #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \ argument
144 (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))
146 #define CN6XXX_SLI_IQ_SIZE(iq) \ argument
147 (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET))
149 #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \ argument
150 (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))
152 #define CN6XXX_SLI_IQ_DOORBELL(iq) \ argument
153 (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET))
155 #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \ argument
156 (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSET))
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H A Docteon_device.c40 /** IQ attributes */
41 .iq = {
149 /** IQ attributes */
150 .iq = {
314 /** IQ attributes */
316 .iq = {
418 /** IQ attributes */
419 .iq = {
532 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
656 if (oct->io_qmask.iq & BIT_ULL(i)) in octeon_free_device_mem()
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H A Dcn23xx_pf_regs.h170 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ argument
171 (CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET))
173 #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \ argument
174 (CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET))
176 #define CN23XX_SLI_IQ_SIZE(iq) \ argument
177 (CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET))
179 #define CN23XX_SLI_IQ_DOORBELL(iq) \ argument
180 (CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET))
182 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ argument
183 (CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSET))
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_main.c62 ioq_vector->iq = oct->iq[i]; in octep_vf_alloc_ioq_vectors()
291 * @iq: Octeon Tx queue data structure.
294 static void octep_vf_enable_ioq_irq(struct octep_vf_iq *iq, struct octep_vf_oq *oq) in octep_vf_enable_ioq_irq() argument
298 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); in octep_vf_enable_ioq_irq()
299 if (iq->pkts_processed) { in octep_vf_enable_ioq_irq()
300 writel(iq->pkts_processed, iq->inst_cnt_reg); in octep_vf_enable_ioq_irq()
301 iq->pkt_in_done -= iq->pkts_processed; in octep_vf_enable_ioq_irq()
302 iq->pkts_processed = 0; in octep_vf_enable_ioq_irq()
312 writeq(1UL << OCTEP_VF_IQ_INTR_RESEND_BIT, iq->inst_cnt_reg); in octep_vf_enable_ioq_irq()
327 tx_pending = octep_vf_iq_process_completions(ioq_vector->iq, 64); in octep_vf_napi_poll()
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H A Doctep_vf_cn9k.c16 /* Dump useful hardware IQ/OQ CSRs for debug purpose */
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
146 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; in octep_vf_init_config_cn93_vf()
147 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; in octep_vf_init_config_cn93_vf()
148 conf->iq.db_min = OCTEP_VF_DB_MIN; in octep_vf_init_config_cn93_vf()
149 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; in octep_vf_init_config_cn93_vf()
163 struct octep_vf_iq *iq = oct->iq[iq_no]; in octep_vf_setup_iq_regs_cn93() local
181 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); in octep_vf_setup_iq_regs_cn93()
182 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); in octep_vf_setup_iq_regs_cn93()
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H A Doctep_vf_cnxk.c16 /* Dump useful hardware IQ/OQ CSRs for debug purpose */
21 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
88 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cnxk_vf_reset_iq()
148 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; in octep_vf_init_config_cnxk_vf()
149 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; in octep_vf_init_config_cnxk_vf()
150 conf->iq.db_min = OCTEP_VF_DB_MIN; in octep_vf_init_config_cnxk_vf()
151 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; in octep_vf_init_config_cnxk_vf()
166 struct octep_vf_iq *iq = oct->iq[iq_no]; in octep_vf_setup_iq_regs_cnxk() local
184 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); in octep_vf_setup_iq_regs_cnxk()
185 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); in octep_vf_setup_iq_regs_cnxk()
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H A Doctep_vf_config.h56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
91 /* Trigger the IQ interrupt when processed cmd count reaches
149 struct octep_vf_iq_config iq; member
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.c65 ioq_vector->iq = oct->iq[i]; in octep_alloc_ioq_vectors()
560 * @iq: Octeon Tx queue data structure.
563 static void octep_enable_ioq_irq(struct octep_iq *iq, struct octep_oq *oq) in octep_enable_ioq_irq() argument
567 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); in octep_enable_ioq_irq()
568 if (iq->pkts_processed) { in octep_enable_ioq_irq()
569 writel(iq->pkts_processed, iq->inst_cnt_reg); in octep_enable_ioq_irq()
570 iq->pkt_in_done -= iq->pkts_processed; in octep_enable_ioq_irq()
571 iq->pkts_processed = 0; in octep_enable_ioq_irq()
581 writeq(1UL << OCTEP_IQ_INTR_RESEND_BIT, iq->inst_cnt_reg); in octep_enable_ioq_irq()
596 tx_pending = octep_iq_process_completions(ioq_vector->iq, budget); in octep_napi_poll()
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H A Doctep_cn9k_pf.c44 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_dump_regs()
112 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cn93_reset_iq()
232 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; in octep_init_config_cn93_pf()
233 conf->iq.instr_type = OCTEP_64BYTE_INSTR; in octep_init_config_cn93_pf()
234 conf->iq.db_min = OCTEP_DB_MIN; in octep_init_config_cn93_pf()
235 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; in octep_init_config_cn93_pf()
265 struct octep_iq *iq = oct->iq[iq_no]; in octep_setup_iq_regs_cn93_pf() local
286 iq->desc_ring_dma); in octep_setup_iq_regs_cn93_pf()
288 iq->max_count); in octep_setup_iq_regs_cn93_pf()
293 iq->doorbell_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cn93_pf()
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H A Doctep_cnxk_pf.c64 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_dump_regs()
132 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cnxk_reset_iq()
251 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; in octep_init_config_cnxk_pf()
252 conf->iq.instr_type = OCTEP_64BYTE_INSTR; in octep_init_config_cnxk_pf()
253 conf->iq.db_min = OCTEP_DB_MIN; in octep_init_config_cnxk_pf()
254 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; in octep_init_config_cnxk_pf()
285 struct octep_iq *iq = oct->iq[iq_no]; in octep_setup_iq_regs_cnxk_pf() local
306 iq->desc_ring_dma); in octep_setup_iq_regs_cnxk_pf()
308 iq->max_count); in octep_setup_iq_regs_cnxk_pf()
313 iq->doorbell_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cnxk_pf()
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H A Doctep_config.h60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
106 /* Trigger the IQ interrupt when processed cmd count reaches
232 struct octep_iq_config iq; member
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A Dpipeline.json10 …"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB…
15 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being proce…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json9 …sued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there i…
12 …sued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there i…
15 …issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there i…
18 …issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there i…
21 …ue to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there i…
24 …ue to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there i…
/linux/drivers/scsi/csiostor/
H A Dcsio_isr.c203 * @iq: Ingress queue pointer.
205 * Processes SCSI completions on the SCSI IQ indicated by scm->iq_idx
212 csio_scsi_isr_handler(struct csio_q *iq) in csio_scsi_isr_handler() argument
214 struct csio_hw *hw = (struct csio_hw *)iq->owner; in csio_scsi_isr_handler()
223 if (unlikely(csio_wr_process_iq(hw, iq, csio_process_scsi_cmpl, in csio_scsi_isr_handler()
258 struct csio_q *iq = (struct csio_q *) dev_id; in csio_scsi_isr() local
261 if (unlikely(!iq)) in csio_scsi_isr()
264 hw = (struct csio_hw *)iq->owner; in csio_scsi_isr()
271 csio_scsi_isr_handler(iq); in csio_scsi_isr()
288 struct csio_q *iq = priv; in csio_scsi_intx_handler() local
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H A Dcsio_wr.h360 iq_handler_t iq_intx_handler; /* IQ INTx handler routine */
410 struct csio_iq iq; member
444 uint32_t fw_iq_start; /* Start ID of IQ for this fn*/
447 /* IQ-id to IQ map table. */
463 #define csio_q_iqid(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->un.iq.iqid)
465 ((__hw)->wrm.q_arr[(__idx)]->un.iq.physiqid)
467 ((__hw)->wrm.q_arr[(__idx)]->un.iq.flq_idx)
473 #define csio_iq_has_fl(__iq) ((__iq)->un.iq.flq_idx != -1)
476 csio_q_flid((__hw), (__hw)->wrm.q_arr[(__iq_qidx)]->un.iq.flq_idx)
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_calib.c56 "starting IQ Mismatch Calibration\n"); in ar9003_hw_setup_calibration()
179 /* Accumulate IQ cal measures for active chains */ in ar9003_hw_iqcal_collect()
216 "Starting IQ Cal and Correction for Chain %d\n", i); in ar9003_hw_iqcalibrate()
296 "IQ Cal and Correction done for Chain %d\n", i); in ar9003_hw_iqcalibrate()
303 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n", in ar9003_hw_iqcalibrate()
347 * Clear offset and IQ calibration, run AGC cal. in ar9003_hw_dynamic_osdac_selection()
549 * solve 4x4 linear equation used in loopback iq cal.
754 /* calculate IQ mismatch */ in ar9003_hw_calc_iq_corr()
782 /* calculate and quantize Tx IQ correction factor */ in ar9003_hw_calc_iq_corr()
803 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n", in ar9003_hw_calc_iq_corr()
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/linux/Documentation/scsi/
H A Dqlogicfas.rst15 * IQ-PCI
16 * IQ-PCI-10
17 * IQ-PCI-D
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-sdr-cs08.rst10 Complex signed 8-bit IQ sample
17 number consist two parts, called In-phase and Quadrature (IQ). Both I
H A Dpixfmt-sdr-cu08.rst10 Complex unsigned 8-bit IQ sample
17 number consist two parts, called In-phase and Quadrature (IQ). Both I

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