| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
23 an IOMMU.
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
28 For arm-smmu binding, see:
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
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| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | qcom,iommu.txt | 1 * QCOM IOMMU v1 Implementation
3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
17 - clock-names : Should be a pair of "iface" (required for IOMMUs
21 - clocks : Phandles for respective clocks described by
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| H A D | msm,iommu-v0.txt | 1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
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| H A D | mediatek,iommu.txt | 1 * Mediatek IOMMU Architecture Implementation
6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
36 +-----+-----+ +----+----+
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| /freebsd/sys/x86/iommu/ |
| H A D | amd_cmd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 #include <dev/iommu/busdma_iommu.h>
57 #include <x86/iommu/amd_reg.h>
58 #include <x86/iommu/x86_iommu.h>
59 #include <x86/iommu/amd_iommu.h>
66 unit->hw_ctrl |= AMDIOMMU_CTRL_CMDBUF_EN; in amdiommu_enable_cmdbuf()
67 amdiommu_write8(unit, AMDIOMMU_CTRL, unit->hw_ctrl); in amdiommu_enable_cmdbuf()
75 unit->hw_ctrl &= ~AMDIOMMU_CTRL_CMDBUF_EN; in amdiommu_disable_cmdbuf()
76 amdiommu_write8(unit, AMDIOMMU_CTRL, unit->hw_ctrl); in amdiommu_disable_cmdbuf()
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| H A D | intel_qi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 #include <dev/iommu/busdma_iommu.h>
57 #include <x86/iommu/intel_reg.h>
58 #include <x86/iommu/x86_iommu.h>
59 #include <x86/iommu/intel_dmar.h>
67 unit->hw_gcmd |= DMAR_GCMD_QIE; in dmar_enable_qi()
68 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_enable_qi()
80 unit->hw_gcmd &= ~DMAR_GCMD_QIE; in dmar_disable_qi()
81 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_disable_qi()
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| H A D | iommu_utils.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
66 #include <dev/iommu/busdma_iommu.h>
67 #include <dev/iommu/iommu.h>
68 #include <x86/iommu/x86_iommu.h>
69 #include <x86/iommu/iommu_intrmap.h>
101 if (zeroed && (m->flags & PG_ZERO) == 0) in iommu_pgalloc()
127 SLIST_INSERT_HEAD(&entry->pgtbl_free, m, plinks.s.ss); in iommu_pgfree()
164 iommu_pgfree(obj, m->pindex, flags | IOMMU_PGF_OBJL, in iommu_map_pgtbl()
194 "Count of pages used for IOMMU pagetables");
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| H A D | intel_ctx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
66 #include <dev/iommu/busdma_iommu.h>
67 #include <x86/iommu/intel_reg.h>
68 #include <x86/iommu/x86_iommu.h>
69 #include <x86/iommu/intel_dmar.h>
90 ctxm = iommu_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_NOALLOC); in dmar_ensure_ctx_page()
101 ctxm = iommu_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_ZERO | in dmar_ensure_ctx_page()
103 re = iommu_map_pgtbl(dmar->ctx_obj, 0, IOMMU_PGF_NOALLOC, &sf); in dmar_ensure_ctx_page()
105 dmar_pte_store(&re->r1, DMAR_ROOT_R1_P | (DMAR_ROOT_R1_CTP_MASK & in dmar_ensure_ctx_page()
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| H A D | x86_iommu.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015, 2024 The FreeBSD Foundation
40 #define IOMMU_PAGE_MASK (IOMMU_PAGE_SIZE - 1)
44 #define IOMMU_PTEMASK (IOMMU_NPTEPG - 1)
67 iommu_unit *iommu);
68 void (*unit_pre_instantiate_ctx)(struct iommu_unit *iommu);
74 iommu_gaddr_t base, iommu_gaddr_t size, struct iommu_qi_genseq *
80 struct iommu_ctx *(*get_ctx)(struct iommu_unit *iommu,
82 void (*free_ctx_locked)(struct iommu_unit *iommu,
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| H A D | amd_idpgtbl.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
66 #include <dev/iommu/busdma_iommu.h>
67 #include <x86/iommu/amd_reg.h>
68 #include <x86/iommu/x86_iommu.h>
69 #include <x86/iommu/amd_iommu.h>
72 iommu_gaddr_t base, int lvl, int flags, iommu_pte_t *pte,
75 iommu_gaddr_t base, iommu_gaddr_t size, int flags,
84 KASSERT(domain->pgtbl_obj == NULL, in amdiommu_domain_alloc_pgtbl()
87 domain->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL, in amdiommu_domain_alloc_pgtbl()
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| H A D | intel_idpgtbl.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
67 #include <dev/iommu/busdma_iommu.h>
68 #include <x86/iommu/intel_reg.h>
69 #include <x86/iommu/x86_iommu.h>
70 #include <x86/iommu/intel_dmar.h>
73 iommu_gaddr_t base, iommu_gaddr_t size, int flags,
91 level, it is non-zero if superpages
105 * - lvl is the level to build;
106 * - idx is the index of the page table page in the pgtbl_obj, which is
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| H A D | intel_dmar.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
34 #include <dev/iommu/iommu.h>
40 * (u) - Protected by iommu unit lock
41 * (d) - Protected by domain lock
42 * (c) - Immutable after initialization
46 * The domain abstraction. Most non-constant members of the domain
77 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj)
78 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
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| H A D | intel_drv.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
71 #include <dev/iommu/busdma_iommu.h>
72 #include <x86/iommu/intel_reg.h>
73 #include <x86/iommu/x86_iommu.h>
74 #include <x86/iommu/intel_dmar.h>
105 ptrend = (char *)dmartbl + dmartbl->Header.Length; in dmar_iterate_tbl()
110 if (dmarh->Length <= 0) { in dmar_iterate_tbl()
112 dmarh->Length); in dmar_iterate_tbl()
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| /freebsd/sys/amd64/vmm/amd/ |
| H A D | amdvi_priv.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 ((1 << (((n) - (m)) + 1)) - 1))
43 * IOMMU PCI capability.
52 * IOMMU extended features.
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
68 * NOTE: Must be 256-bits/32 bytes aligned.
98 uint64_t intmap_base:46; /* IntMap base. */
112 * IOMMU command entry.
127 #define AMDVI_PREFETCH_PAGES_OPCODE 0x6 /* Prefetch IOMMU pages. */
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| /freebsd/sys/contrib/device-tree/Bindings/virtio/ |
| H A D | mmio.txt | 3 See https://ozlabs.org/~rusty/virtio-spec/ for more details.
7 - compatible: "virtio,mmio" compatibility string
8 - reg: control registers base address and size including configuration space
9 - interrupts: interrupt generated by the device
11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
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| /freebsd/sys/arm64/iommu/ |
| H A D | iommu.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
54 #include <dev/iommu/busdma_iommu.h>
63 #include "iommu.h"
66 static MALLOC_DEFINE(M_IOMMU, "IOMMU", "IOMMU framework");
77 struct iommu_unit *iommu; member
86 struct iommu_unit *iommu; in iommu_domain_unmap_buf() local
89 iommu = iodom->iommu; in iommu_domain_unmap_buf()
90 error = IOMMU_UNMAP(iommu->dev, iodom, entry->start, entry->end - in iommu_domain_unmap_buf()
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | mediatek,smi-common.txt | 3 The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
11 register which control the iommu port is at each larb's register base. But
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
20 "mediatek,mt2712-smi-common"
21 "mediatek,mt6779-smi-common"
22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 "mediatek,mt8167-smi-common"
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| H A D | mediatek,smi-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | mediatek-vcodec.txt | 7 - compatible : must be one of the following string:
8 "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9 "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12 "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13 "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
14 "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
15 - reg : Physical base address of the video codec registers and length of
17 - interrupts : interrupt number to the cpu.
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| H A D | mediatek-jpeg-decoder.txt | 6 - compatible : must be one of the following string:
7 "mediatek,mt8173-jpgdec"
8 "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
9 "mediatek,mt2701-jpgdec"
10 - reg : physical base address of the jpeg decoder registers and length of
12 - interrupts : interrupt number to the interrupt controller.
13 - clocks: device clocks, see
14 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "jpgdec-smi" and "jpgdec".
16 - power-domains: a phandle to the power domain, see
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| H A D | mediatek-jpeg-encoder.txt | 6 - compatible : "mediatek,mt2701-jpgenc"
7 followed by "mediatek,mtk-jpgenc"
8 - reg : physical base address of the JPEG encoder registers and length of
10 - interrupts : interrupt number to the interrupt controller.
11 - clocks: device clocks, see
12 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
14 - power-domains: a phandle to the power domain, see
16 - mediatek,larb: must contain the local arbiters in the current SoCs, see
17 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
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| H A D | mediatek-mdp.txt | 6 - compatible: "mediatek,mt8173-mdp"
7 - mediatek,vpu: the node of video processor unit, see
8 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
11 - compatible: Should be one of
12 "mediatek,mt8173-mdp-rdma" - read DMA
13 "mediatek,mt8173-mdp-rsz" - resizer
14 "mediatek,mt8173-mdp-wdma" - write DMA
15 "mediatek,mt8173-mdp-wrot" - write DMA with rotation
16 - reg: Physical base address and length of the function block register space
17 - clocks: device clocks, see
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | arm,komeda.txt | 4 - compatible: Should be "arm,mali-d71"
5 - reg: Physical base address and length of the registers in the system
6 - interrupts: the interrupt line number of the device in the system
7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
8 in 'clock-names'
9 - clock-names: A list of clock names. It should contain:
10 - "aclk": for the main processor clock
11 - #address-cells: Must be 1
12 - #size-cells: Must be 0
13 - iommus: configure the stream id to IOMMU, Must be configured if want to
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