Lines Matching +full:iommu +full:- +full:base

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2013-2015 The FreeBSD Foundation
34 #include <dev/iommu/iommu.h>
40  * (u) - Protected by iommu unit lock
41  * (d) - Protected by domain lock
42  * (c) - Immutable after initialization
46  * The domain abstraction.  Most non-constant members of the domain
77 #define	DMAR_DOMAIN_PGLOCK(dom)		VM_OBJECT_WLOCK((dom)->pgtbl_obj)
78 #define	DMAR_DOMAIN_PGTRYLOCK(dom)	VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
79 #define	DMAR_DOMAIN_PGUNLOCK(dom)	VM_OBJECT_WUNLOCK((dom)->pgtbl_obj)
81 	VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj)
83 #define	DMAR_DOMAIN_LOCK(dom)	mtx_lock(&(dom)->iodom.lock)
84 #define	DMAR_DOMAIN_UNLOCK(dom)	mtx_unlock(&(dom)->iodom.lock)
85 #define	DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED)
87 #define	DMAR2IOMMU(dmar)	(&((dmar)->iommu))
89 	__containerof((dmar), struct dmar_unit, iommu)
91 #define	DOM2IODOM(domain)	(&((domain)->iodom))
95 #define	CTX2IOCTX(ctx)		(&((ctx)->context))
99 #define	CTX2DOM(ctx)		IODOM2DOM((ctx)->context.domain)
100 #define	CTX2DMAR(ctx)		(CTX2DOM(ctx)->dmar)
101 #define	DOM2DMAR(domain)	((domain)->dmar)
108 	struct iommu_unit iommu;  member
111 	uint64_t base;  member
150 #define	DMAR_LOCK(dmar)		mtx_lock(&DMAR2IOMMU(dmar)->lock)
151 #define	DMAR_UNLOCK(dmar)	mtx_unlock(&DMAR2IOMMU(dmar)->lock)
152 #define	DMAR_ASSERT_LOCKED(dmar) mtx_assert(&DMAR2IOMMU(dmar)->lock, MA_OWNED)
154 #define	DMAR_FAULT_LOCK(dmar)	mtx_lock_spin(&(dmar)->fault_lock)
155 #define	DMAR_FAULT_UNLOCK(dmar)	mtx_unlock_spin(&(dmar)->fault_lock)
156 #define	DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
158 #define	DMAR_IS_COHERENT(dmar)	(((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
159 #define	DMAR_HAS_QI(dmar)	(((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
161 	(x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
180 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size,
223 void dmar_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base,
241 struct iommu_ctx *dmar_get_ctx(struct iommu_unit *iommu, device_t dev,
275 	return (bus_read_4(unit->regs, reg));  in dmar_read4()
284 	low = bus_read_4(unit->regs, reg);  in dmar_read8()
285 	high = bus_read_4(unit->regs, reg + 4);  in dmar_read8()
288 	return (bus_read_8(unit->regs, reg));  in dmar_read8()
297 	    (unit->hw_gcmd & DMAR_GCMD_TE),  in dmar_write4()
298 	    ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit,  in dmar_write4()
299 	    unit->hw_gcmd, val));  in dmar_write4()
300 	bus_write_4(unit->regs, reg, val);  in dmar_write4()
313 	bus_write_4(unit->regs, reg, low);  in dmar_write8()
314 	bus_write_4(unit->regs, reg + 4, high);  in dmar_write8()
316 	bus_write_8(unit->regs, reg, val);  in dmar_write8()
418 	old_td_pinned = curthread->td_pinned
420 	KASSERT(curthread->td_pinned == old_td_pinned,			\
421 	    ("pin count leak: %d %d %s:%d", curthread->td_pinned,	\