Lines Matching +full:iommu +full:- +full:base
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 ((1 << (((n) - (m)) + 1)) - 1))
43 * IOMMU PCI capability.
52 * IOMMU extended features.
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
68 * NOTE: Must be 256-bits/32 bytes aligned.
98 uint64_t intmap_base:46; /* IntMap base. */
112 * IOMMU command entry.
127 #define AMDVI_PREFETCH_PAGES_OPCODE 0x6 /* Prefetch IOMMU pages. */
151 * IOMMU event entry.
179 * IOMMU control block.
185 uint64_t base:40; /* Devtable register base. */ member
190 uint64_t base:40; member
197 uint64_t base:40; member
208 uint64_t base:40; member
220 uint64_t base:40; member
257 * AMF IOMMU v2 size including event counters
271 #define IVHD_FLAG_PFS BIT(6) /* Prefetch IOMMU pages. */
283 /* IVHD 8-byte extended data settings. */
286 /* IOMMU control register. */
287 #define AMDVI_CTRL_EN BIT(0) /* IOMMU enable. */
318 /* Maximum number of domains supported by IOMMU. */
319 #define AMDVI_MAX_DOMAIN (BIT(16) - 1)
322 * IOMMU Page Table attributes.
335 * IOMMU Status, offset 0x2020
374 * AMD IOMMU softc.
378 device_t dev; /* IOMMU device. */
379 device_t pci_dev; /* IOMMU PCI function device. */
380 enum IvrsType ivhd_type; /* IOMMU IVHD type. */
381 bool iotlb; /* IOTLB supported by IOMMU */
394 uint16_t pci_seg; /* IOMMU PCI domain/segment. */
395 uint16_t pci_rid; /* PCI BDF of IOMMU */