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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-imx-uart.txt4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
20 and RTS_B is input, regardless of dte-mode.
[all …]
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-im
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dklondike.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dmakalu.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dkilauea.dts4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-prog {
41 wakeup-source;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dazoteq,iqs7211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control-
14 lers employ projected-capacitance sensing and can track two contacts.
21 - azoteq,iqs7210a
22 - azoteq,iqs7211a
23 - azoteq,iqs7211e
28 irq-gpios:
[all …]
/freebsd/sys/dev/mii/
H A Dnsphyterreg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
62 #define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
87 #define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
113 #define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */
133 #define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
150 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
[all …]
H A Dmcommphy.c98 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
141 * different TX inverted configuration depending on speed used in mcommphy_service()
143 if (sc->mii_mpd_model == MCOMMPHY_YT8531_MODEL && in mcommphy_service()
144 (sc->mii_media_active != mii->mii_media_active || in mcommphy_service()
145 sc->mii_media_status != mii->mii_media_status)) { in mcommphy_service()
170 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MCOMMPHY_YT8511_OUI && in mcommphy_probe()
171 MII_MODEL(ma->mii_id2) == MCOMMPHY_YT8511_MODEL && in mcommphy_probe()
172 MII_REV(ma->mii_id2) == MCOMMPHY_YT8511_REV) { in mcommphy_probe()
192 if (sc->mii_flags & MIIF_RX_DELAY) { in mcommphy_yt8511_setup()
198 if (sc->mii_flags & MIIF_TX_DELAY) { in mcommphy_yt8511_setup()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/rmi4/
H A Drmi_spi.txt10 - compatible: syna,rmi4-spi
11 - reg: Chip select address for the device
12 - #address-cells: Set to 1 to indicate that the function child nodes
14 - #size-cells: Set to 0 to indicate that the function child nodes do not
18 - interrupts: interrupt which the rmi device is connected to.
19 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
33 rmi4-spi-dev@0 {
34 compatible = "syna,rmi4-spi";
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/sve/
H A Dsv_sincospi_common.h2 * Core approximation for double-precision SVE sincospi
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
20 .c1 = -0x1.4abbce625be53p2,
22 .c3 = -0x1.32d2cce62dc33p-1,
23 .c4 = 0x1.507834891188ep-4,
24 .c5 = -0x1.e30750a28c88ep-8,
25 .c6 = 0x1.e8f48308acda4p-12,
26 .c7 = -0x1.6fc0032b3c29fp-16,
27 .c8 = 0x1.af86ae521260bp-21,
28 .c9 = -0x1.012a9870eeb7dp-25,
[all …]
H A Dsv_sincospif_common.h2 * Helper for single-precision SVE sincospi
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19 .c1 = -0x1.4abbcep2f,
21 .c3 = -0x1.32d2ccp-1f,
22 .c4 = 0x1.50783p-4f,
23 .c5 = -0x1.e30750p-8f,
28 /* Single-precision vector function allowing calculation of both sinpi and
30 Worst-case error for sin is 3.04 ULP:
31 _ZGVsMxvl4l4_sincospif_sin(0x1.b51b8p-2) got 0x1.f28b5ep-1 want
32 0x1.f28b58p-1.
[all …]
/freebsd/share/man/man4/
H A Duart.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
59 set RX FIFO trigger level to ``low'' (NS8250 only)
61 set RX FIFO trigger level to ``medium low'' (NS8250 only)
63 set RX FIFO trigger level to ``medium high'' (default, NS8250 only)
65 set RX FIFO trigger level to ``high'' (NS8250 only)
72 EIA RS-232C (CCITT V.24) serial communications interface.
112 It contains the bus attachments and the low-level interrupt handler.
144 .Bl -bullet -compact
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/freebsd/sys/contrib/dev/athk/
H A Dkey.c25 #define REG_READ (common->ops->read)
26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
28 if (common->ops->enable_write_buffer) \
29 common->ops->enable_write_buffer((_ah));
32 if (common->ops->write_flush) \
33 common->ops->write_flush((_ah));
45 void *ah = common->ah; in ath_hw_keyreset()
47 if (entry >= common->keymax) { in ath_hw_keyreset()
73 if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) { in ath_hw_keyreset()
91 void *ah = common->ah; in ath_hw_keysetmac()
[all …]

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