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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,rzg2l-irqc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
37 '#interrupt-cells':
39 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
46 interrupt-controller: true
55 interrupt-names:
60 - description: NMI interrupt
[all...]
H A Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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H A Dsamsung,exynos4210-combiner.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
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H A Dfsl,ls-extirq.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
7 title: Freescale Layerscape External Interrupt Controller
14 LX216xA) support inverting the polarity of certain external interrupt
34 '#interrupt-cells':
40 interrupt-controller: true
45 Specifies the Interrupt Polarity Control Register (INTPCR) in the
46 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
48 interrupt-map:
51 interrupt-map-mask: true
55 - '#interrupt-cells'
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/linux/drivers/net/ipa/
H A Dipa_interrupt.c9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
22 #include <linux/interrupt.h>
36 * struct ipa_interrupt - IPA interrupt information
40 * @suspend_enabled: Bitmap of endpoints with the SUSPEND interrupt enabled
49 /* Clear the suspend interrupt for all endpoints that signaled it */
50 static void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) in ipa_interrupt_suspend_clear_all() argument
52 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_suspend_clear_all()
64 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ in ipa_interrupt_suspend_clear_all()
73 /* Process a particular interrupt type that has been received */
[all …]
H A Dipa_interrupt.h20 * @interrupt: IPA interrupt structure
21 * @endpoint_id: Endpoint whose interrupt should be enabled
24 * A TX_SUSPEND interrupt arrives on an AP RX enpoint when packet data can't
28 void ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt,
33 * @interrupt: IPA interrupt structure
34 * @endpoint_id: Endpoint whose interrupt should be disabled
36 void ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt,
40 * ipa_interrupt_simulate_suspend() - Simulate TX_SUSPEND IPA interrupt
41 * @interrupt: IPA interrupt structure
43 * This calls the TX_SUSPEND interrupt handler, as if such an interrupt
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
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/linux/arch/powerpc/boot/dts/
H A Dfsp2.dts64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
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/linux/arch/mips/boot/dts/brcm/
H A Dbcm7358.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7360.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7346.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
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H A Dbcm7362.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7425.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7435.dtsi42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
H A Dbcm7125.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
H A Dbcm7420.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
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/linux/sound/soc/sdca/
H A Dsdca_interrupts.c15 #include <linux/interrupt.h>
83 struct sdca_interrupt *interrupt = data; in base_handler() local
84 struct device *dev = interrupt->dev; in base_handler()
86 dev_info(dev, "%s irq without full handling\n", interrupt->name); in base_handler()
93 struct sdca_interrupt *interrupt = data; in function_status_handler() local
94 struct device *dev = interrupt->dev; in function_status_handler()
107 reg = SDW_SDCA_CTL(interrupt->function->desc->adr, interrupt->entity->id, in function_status_handler()
108 interrupt->control->sel, 0); in function_status_handler()
110 ret = regmap_read(interrupt in function_status_handler()
155 struct sdca_interrupt *interrupt = data; detected_mode_handler() local
178 struct sdca_interrupt *interrupt = data; hid_handler() local
213 struct sdca_interrupt *interrupt = data; fdl_owner_handler() local
359 sdca_irq_data_populate(struct device * dev,struct regmap * regmap,struct snd_soc_component * component,struct sdca_function_data * function,struct sdca_entity * entity,struct sdca_control * control,struct sdca_interrupt * interrupt) sdca_irq_data_populate() argument
433 struct sdca_interrupt *interrupt; sdca_irq_populate_early() local
499 struct sdca_interrupt *interrupt; sdca_irq_populate() local
573 struct sdca_interrupt *interrupt = &info->irqs[i]; sdca_irq_cleanup() local
633 struct sdca_interrupt *interrupt; irq_enable_flags() local
692 struct sdca_interrupt *interrupt; sdca_irq_disable() local
[all...]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi8 #include <dt-bindings/interrupt-controller/irq.h>
41 cpuintc: interrupt-controller {
42 compatible = "loongson,cpu-interrupt-controller";
43 #interrupt-cells = <1>;
44 interrupt-controller;
96 interrupt-parent = <&eiointc>;
119 interrupt-parent = <&liointc>;
124 liointc: interrupt-controller@1fe01400 {
128 interrupt-controller;
130 #interrupt-cells = <2>;
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi122 interrupt-names = "intx";
124 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
138 pcie1_intc: interrupt-controller {
139 interrupt-controller;
140 #interrupt-cells = <1>;
150 interrupt-names = "intx";
152 #interrupt-cells = <1>;
156 interrupt-map-mask = <0 0 0 7>;
[all …]
H A Darmada-xp-mv78260.dtsi101 interrupt-names = "intx";
103 #interrupt-cells = <1>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
117 pcie1_intc: interrupt-controller {
118 interrupt-controller;
119 #interrupt-cells = <1>;
129 interrupt-names = "intx";
131 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 7>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi5 #include <dt-bindings/interrupt-controller/irq.h>
32 cpuintc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
36 compatible = "mti,cpu-interrupt-controller";
59 liointc0: interrupt-controller@1fe11400 {
66 interrupt-controller;
67 #interrupt-cells = <2>;
69 interrupt-parent = <&cpuintc>;
71 interrupt-names = "int0";
[all …]
/linux/include/linux/pds/
H A Dpds_intr.h8 * Interrupt control register
16 * When an interrupt is sent the interrupt
22 * interrupt coalescing is effectively disabled
23 * and every interrupt assert results in an
24 * interrupt. Reset value: 0
25 * @mask: Interrupt mask. When @mask=1 the interrupt
26 * resource will not send an interrupt. When
27 * @mask=0 the interrupt resource will send an
28 * interrupt if an interrupt event is pending
29 * or on the next interrupt assertion event.
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dxlnx,nwl-pcie.yaml14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
34 - description: interrupt asserted when miscellaneous interrupt is received
35 - description: unused interrupt(dummy)
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
40 interrupt-names:
48 interrupt-map-mask:
55 "#interrupt-cells":
61 interrupt-map:
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H A Dxlnx,xdma-host.yaml38 - description: interrupt asserted when miscellaneous interrupt is received.
39 - description: msi0 interrupt asserted when an MSI is received.
40 - description: msi1 interrupt asserted when an MSI is received.
42 interrupt-names:
48 interrupt-map-mask:
55 interrupt-map:
58 "#interrupt-cells":
61 interrupt-controller:
62 description: identifies the node as an interrupt controller
65 interrupt-controller: true
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