| /linux/sound/soc/sdca/ |
| H A D | sdca_jack.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * https://www.mipi.org/mipi-sdca-v1-0-download
25 #include <sound/soc-component.h>
26 #include <sound/soc-jack.h>
30 * sdca_jack_process - Process an SDCA jack event
31 * @interrupt: SDCA interrupt structure
35 int sdca_jack_process(struct sdca_interrupt *interrupt) in sdca_jack_process() argument
37 struct device *dev = interrupt->dev; in sdca_jack_process()
38 struct snd_soc_component *component = interrupt->component; in sdca_jack_process()
39 struct snd_soc_card *card = component->card; in sdca_jack_process()
[all …]
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | stericsson,ab8500.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linusw@kernel.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
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| H A D | stericsson,db8500-prcmu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit
10 - Linus Walleij <linusw@kernel.org>
13 The DB8500 Power Reset and Control Management Unit is an XP70 8-bit
14 microprocessor that is embedded in the always-on power domain of the
20 pattern: '^prcmu@[0-9a-f]+$'
23 description: The device is compatible both to the device-specific
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_irq.c | 30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
153 * amdgpu_irq_disable_all - disable *all* interrupts
165 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
167 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
171 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
173 if (!src || !src->funcs->set || !src->num_types) in amdgpu_irq_disable_all()
[all …]
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| /linux/Documentation/core-api/ |
| H A D | genericirq.rst | 7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
13 The generic interrupt handling layer is designed to provide a complete
14 abstraction of interrupt handling for device drivers. It is able to
15 handle all the different types of interrupt controller hardware. Device
17 interrupts. The drivers do not have to know anything about interrupt
22 interrupt subsystem based for their architecture, with the help of the
28 The original implementation of interrupt handling in Linux uses the
29 __do_IRQ() super-handler, which is able to deal with every type of
30 interrupt logic.
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | xlnx,intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Interrupt Controller
10 - Michal Simek <michal.simek@amd.com>
14 number of interrupts and the type of each interrupt. These details cannot
19 const: xlnx,xps-intc-1.00.a
27 power-domains:
33 "#interrupt-cells":
[all …]
|
| H A D | arm,gic-v5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 5
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
15 compliant interrupt controllers for AArch64 systems.
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | srio-rmu.txt | 5 node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6 "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
10 - compatible
12 Value type: <string>
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
18 - reg
20 Value type: <prop-encoded-array>
25 - fsl,liodn
26 Usage: optional-but-recommended (for devices with PAMU)
27 Value type: <prop-encoded-array>
[all …]
|
| H A D | dcsr.txt | 21 - compatible
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
29 Value type: <u32>
33 - #size-cells
35 Value type: <u32>
40 - ranges
42 Value type: <prop-encoded-array>
[all …]
|
| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | param.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
15 #define OPTION_UNSET -1
36 /* Transmit Interrupt Delay in units of 1.024 microseconds
37 * Tx interrupt delay needs to typically be set to something non-zero
39 * Valid Range: 0-65535
41 E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
46 /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
48 * Valid Range: 0-65535
50 E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | mediatek,mt6893-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
17 const: mediatek,mt6893-pinctrl
21 - description: pin controller base
22 - description: rm group IO
23 - description: bm group IO
24 - description: lm group IO
[all …]
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| H A D | mediatek,mt8186-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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|
| H A D | mediatek,mt8195-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
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| H A D | mediatek,mt8196-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lei Xue <lei.xue@mediatek.com>
11 - Cathy Xu <ot_cathy.xu@mediatek.com>
18 const: mediatek,mt8196-pinctrl
22 - description: gpio base
23 - description: rt group IO
24 - description: rm1 group IO
[all …]
|
| H A D | mediatek,mt6878-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Igor Belwon <igor.belwon@mentallysanemainliners.org>
18 const: mediatek,mt6878-pinctrl
22 - description: pin controller base
23 - description: bl group IO
24 - description: bm group IO
[all …]
|
| H A D | mediatek,mt8189-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lei Xue <lei.xue@mediatek.com>
11 - Cathy Xu <ot_cathy.xu@mediatek.com>
18 const: mediatek,mt8189-pinctrl
22 - description: gpio base
23 - description: lm group IO
24 - description: rb0 group IO
[all …]
|
| H A D | mediatek,mt8192-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
|
| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
|
| /linux/arch/powerpc/platforms/52xx/ |
| H A D | mpc52xx_pic.c | 3 * Programmable Interrupt Controller functions for the Freescale MPC52xx.
20 * This is the device driver for the MPC5200 interrupt controller.
23 * -----------------
24 * The MPC5200 interrupt controller groups the all interrupt sources into
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
36 * systems can have multiple interrupt controllers, the virtual IRQ (virq)
37 * infrastructure lets each interrupt controller to define a local set
48 * For example, the TMR0 interrupt is irq 9 in the main group. The
52 * interrupt group called 'bestcomm'. The bestcomm group isn't physically
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | irq-ixp4xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * irqchip for the IXP4xx interrupt controller
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
26 #define IXP4XX_ICPR 0x00 /* Interrupt Status */
27 #define IXP4XX_ICMR 0x04 /* Interrupt Enable */
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
31 #define IXP4XX_ICHR 0x14 /* Interrupt Priority */
35 /* IXP43x and IXP46x-only */
36 #define IXP4XX_ICPR2 0x20 /* Interrupt Status 2 */
[all …]
|
| /linux/rust/kernel/irq/ |
| H A D | flags.rs | 1 // SPDX-License-Identifier: GPL-2.0
2 // SPDX-FileCopyrightText: Copyright 2025 Collabora ltd.
13 /// A common use case is to register a shared interrupt, as sharing the line
16 /// requesting the interrupt. Other use cases include setting the trigger type
17 /// through `Flags::TRIGGER_*`, which determines when the interrupt fires, or
18 /// controlling whether the interrupt is masked after the handler runs by using
24 /// [`crate::irq::Registration`] for a shared interrupt have to agree on
25 /// [`Flags::SHARED`] and on the same trigger type, if set.
30 /// Use the interrupt line as already configured.
33 /// The interrupt is triggered when the signal goes from low to high.
[all …]
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| /linux/kernel/irq/ |
| H A D | resend.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner
6 * This file contains the IRQ-resend code
8 * If the interrupt is waiting to be processed, we try to re-run it.
10 * interrupt-protected region. Not all irq controller chips can
18 #include <linux/interrupt.h>
38 hlist_del_init(&desc->resend_node); in resend_irqs()
41 desc->handle_irq(desc); in resend_irqs()
52 * Validate whether this interrupt can be safely injected from in irq_sw_resend()
[all …]
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | gpio-keys.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/input/gpio-keys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 - gpio-keys
16 - gpio-keys-polled
23 poll-interval: true
26 …"^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switc…
35 - items:
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | altr-pio-1.0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/altr-pio-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
11 - Marek Vasut <marex@denx.de>
12 - Mathieu Malaterre <malat@debian.org>
13 - Tien Hock Loh <thloh@altera.com>
17 const: altr,pio-1.0
22 gpio-controller: true
[all …]
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
|