Home
last modified time | relevance | path

Searched full:inta (Results 1 – 25 of 53) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,sci-inta.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
16 The Interrupt Aggregator (INTA) provides a centralized machine
55 const: ti,sci-inta
70 Interrupt ranges that converts the INTA output hw irq numbers
75 "output_irq" specifies the base for inta output irq
109 compatible = "ti,sci-inta";
H A Dti,sci-inta.txt4 The Interrupt Aggregator (INTA) provides a centralized machine
40 - compatible: Must be "ti,sci-inta".
47 - ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
48 outputs) range within this INTA, assigned to the
57 compatible = "ti,sci-inta";
H A Dti,sci-intr.yaml29 | INTA |----------->| . . | +-------+
H A Dti,sci-intr.txt17 | INTA |----------->| . . | +-------+
/freebsd/sys/contrib/dev/iwlwifi/pcie/
H A Drx.c1717 u32 inta;
1724 inta = iwl_read32(trans, CSR_INT);
1727 return inta;
1736 * stop using INTA register to get device's interrupt, reading this register
1746 u32 inta;
1791 inta = (0xff & val) | ((0xff00 & val) << 16);
1792 return inta;
1840 u32 inta = 0;
1852 inta = iwl_pcie_int_cause_ict(trans);
1854 inta
[all...]
H A Dtrans-gen2.c45 * Enable HAP INTA (interrupt from management bus) to in iwl_pcie_gen2_apm_init()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.cpp279 /// other than BValNo val# that can reach uses of AValno val# of IntA.
280 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
620 LiveInterval &IntA = in adjustCopiesBackFrom() local
626 // We have a non-trivially-coalescable copy with IntA being the source and in adjustCopiesBackFrom()
628 // source value number (in IntA) is defined by a copy from B, see if we can in adjustCopiesBackFrom()
653 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx); in adjustCopiesBackFrom()
655 if (AS == IntA.end()) return false; in adjustCopiesBackFrom()
733 CopyMI->substituteRegister(IntA.reg(), IntB.reg(), 0, *TRI); in adjustCopiesBackFrom()
738 for (LiveInterval::SubRange &S : IntA.subranges()) { in adjustCopiesBackFrom()
747 shrinkToUses(&IntA); in adjustCopiesBackFrom()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_interrupts.h52 * 2. INTA assert/deassert (RC only).
85 * line that reflects the status of ASSERT/DEASSERT of INTA
96 * line that reflects the status of ASSERT/DEASSERT of INTA
111 /** [RC only] PME Status bit assertion in the Root Status register With INTA */
/freebsd/tools/tools/pirtool/
H A Dpirtable.h50 uint8_t inta_link; /* how INTA is linked */
51 uint16_t inta_irqs; /* how INTA may be routed (bitset) */
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsifive,fu740-pcie.yaml45 - const: inta
107 interrupt-names = "msi", "inta", "intb", "intc", "intd";
H A Dpcie-al.txt44 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
H A Duniphier-pcie.txt71 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
H A Drockchip-dw-pcie-common.yaml60 interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8379_rdb.dts406 /* IDSEL AD14 IRQ6 inta */
409 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
414 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
H A Dmpc8377_rdb.dts392 /* IDSEL AD14 IRQ6 inta */
395 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
400 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
H A Dmpc8378_rdb.dts376 /* IDSEL AD14 IRQ6 inta */
379 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
384 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
H A Dmpc8377_wlan.dts374 /* IDSEL AD14 IRQ6 inta */
377 /* IDSEL AD15 IRQ5 inta */
H A Dholly.dts157 | The INTA, INTB, INTC, INTD are shared.
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt29 - msi-parent : phandle for "ti,sci-inta" interrupt controller
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h408 * control whether the MAC's INTA# output is asserted. The bits in
411 * IMR_S* registers DO NOT determine whether INTA# is asserted.
412 * That is INTA# is asserted only when the logical AND of ISR_P
415 * directly affect whether INTA# is asserted.
481 * Only the bits in the IMR control whether the MAC's INTA#
485 * DO NOT determine whether INTA# is asserted.
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h92 #define BHND_PCI_INTR_A 0x01 /* PCI INTA# is asserted */
176 #define BHND_PCIE_INTR_A BHND_PCI_INTR_A /* PCIE INTA message is received */
/freebsd/sys/dev/acpica/
H A Dacpi_pcib.c165 * (note that ACPI uses 0 for INTA) to check for a match. in prt_lookup_device()
/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu740-c000.dtsi350 interrupt-names = "msi", "inta", "intb", "intc", "intd";
/freebsd/sys/contrib/xen/arch-x86/hvm/
H A Dsave.h337 /* Automatically clear IRQs from the ISR during INTA? */
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62p-j722s-common-main.dtsi85 compatible = "ti,sci-inta";
168 compatible = "ti,sci-inta";

123