Lines Matching full:inta

1717 	u32 inta;
1724 	inta = iwl_read32(trans, CSR_INT);
1727 	return inta;
1736  * stop using INTA register to get device's interrupt, reading this register
1746 	u32 inta;
1791 	inta = (0xff & val) | ((0xff00 & val) << 16);
1792 	return inta;
1840 	u32 inta = 0;
1852 		inta = iwl_pcie_int_cause_ict(trans);
1854 		inta = iwl_pcie_int_cause_non_ict(trans);
1859 			      "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1860 			      inta, trans_pcie->inta_mask,
1863 		if (inta & (~trans_pcie->inta_mask))
1866 				      inta & (~trans_pcie->inta_mask));
1870 	inta &= trans_pcie->inta_mask;
1877 	if (unlikely(!inta)) {
1878 		IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1890 	if (unlikely(inta == 0xFFFFFFFF || iwl_trans_is_hw_error_value(inta))) {
1895 		IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1911 	iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1915 		IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1916 			      inta, iwl_read32(trans, CSR_INT_MASK));
1922 	if (inta & CSR_INT_BIT_HW_ERR) {
1937 	if (inta & CSR_INT_BIT_SCD) {
1944 	if (inta & CSR_INT_BIT_ALIVE) {
1959 	inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1962 	if (inta & CSR_INT_BIT_RF_KILL) {
1968 	if (inta & CSR_INT_BIT_CT_KILL) {
1975 	if (inta & CSR_INT_BIT_SW_ERR) {
1977 			" Restarting 0x%X.\n", inta);
1984 	if (inta & CSR_INT_BIT_WAKEUP) {
1997 	if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
2000 		if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
2005 		if (inta & CSR_INT_BIT_RX_PERIODIC) {
2032 		if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
2047 	if (inta & CSR_INT_BIT_FH_TX) {
2062 	if (inta & ~handled) {
2063 		IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
2067 	if (inta & ~(trans_pcie->inta_mask)) {
2068 		IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
2069 			 inta & ~trans_pcie->inta_mask);
2234 		IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");