| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/ |
| H A D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
47 "BriefDescription": "Number of I-ERAT reloads",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
[all …]
|
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
24 …(prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
29 …cope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
30 …group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
35 … Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
41 …l Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
42 …s chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
47 … all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/ |
| H A D | marked.json | 5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
35 …ption": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflic…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
75 "BriefDescription": "Vector FP instruction completed"
80 …cription": "The processor's Instruction cache was reloaded from local core's L2 without conflict d…
85 …tion": "The processor's Instruction cache was reloaded from a location other than the local core's…
90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
120 …The processor's Instruction cache was reloaded from another chip's memory on the same Node or Grou…
[all …]
|
| H A D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …"The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the…
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
[all …]
|
| H A D | cache.json | 5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of…
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
40 …ocessor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 …
45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
50 … "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group …
55 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node …
90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
[all …]
|
| H A D | other.json | 15 "BriefDescription": "Demand Instruction fetch request"
20 "BriefDescription": "TM resume instruction completed"
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …efDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due t…
110 …"BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go…
135 …n": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): T…
200 "BriefDescription": "Read-write data cache collisions"
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
290 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
[all …]
|
| H A D | pipeline.json | 10 "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
100 …escription": "The NTC instruction is being held at dispatch because it lost arbitration onto the i…
150 "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch"
195 …n=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
200 "BriefDescription": "Non-speculative icache miss, counted at completion"
240 …Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
255 …"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruct…
275 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating P…
315 "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/icelake/ |
| H A D | frontend.json | 9 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
35 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
80 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
86 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
95 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| H A D | virtual-memory.json | 149 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
155 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
161 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
168 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
180 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
192 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
204 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
216 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
222 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
228 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/ |
| H A D | frontend.json | 9 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
14 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
27 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
47 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
62 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
77 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
83 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
92 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| H A D | virtual-memory.json | 137 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
143 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
148 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
155 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
166 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
177 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
188 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
199 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
204 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
210 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/ |
| H A D | frontend.json | 9 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
35 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
80 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
86 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
95 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| H A D | virtual-memory.json | 173 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
179 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
185 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
192 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
204 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
216 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
228 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
240 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
246 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
252 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/ |
| H A D | virtual-memory.json | 159 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
165 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
170 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
177 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
188 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
199 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
210 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
221 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 175 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
180 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
190 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
195 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
204 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
210 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
220 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
230 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
240 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
250 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| H A D | frontend.json | 8 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
69 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 175 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
180 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
190 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
195 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
204 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
210 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
220 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
230 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
240 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
250 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| H A D | frontend.json | 8 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
69 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 175 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
180 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
190 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
195 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
204 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
210 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
220 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
230 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
240 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
250 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| H A D | frontend.json | 8 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
69 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/ |
| H A D | virtual-memory.json | 106 …t during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to…
118 … to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address…
123 "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page",
130 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
135 "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page",
142 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
147 "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page",
154 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
159 "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle.",
166 …ion": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cy…
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/ |
| H A D | virtual-memory.json | 8 … to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address…
49 "BriefDescription": "Duration of page-walks in cycles",
54 …n": "Counts every core cycle a page-walk is in progress due to either a data memory operation or a…
59 "BriefDescription": "Duration of D-side page-walks in cycles",
64 …"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) pag…
69 "BriefDescription": "Duration of I-side pagewalks in cycles",
74 …ublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction f…
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| H A D | cache.json | 3 "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This…
23 … instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetc…
27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.…
31 …counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to t…
39 …"PublicDescription": "This event counts any write-back of data from the L2 cache to outside the co…
43 …the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line wr…
52 …"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TL…
54 "BriefDescription": "Level 1 instruction TLB access"
57 …the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line wr…
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | virtual-memory.json | 79 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
161 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
233 …he number of times the machine was unable to find a translation in the Instruction Translation Loo…
238 …"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE…
249 …he number of first level TLB misses but second level hits due to an instruction fetch that did not…
260 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
266 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
271 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
278 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
283 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | microchip,pic32-dmt.txt | 4 malfunction. It is a free-running instruction fetch timer, which is clocked
5 whenever an instruction fetch occurs until a count match occurs.
8 - compatible: must be "microchip,pic32mzda-dmt".
9 - reg: physical base address of the controller and length of memory mapped
11 - clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
16 compatible = "microchip,pic32mzda-dmt";
|