Lines Matching +full:instruction +full:- +full:fetch

8 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
13         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
69 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
75         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
88         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
101         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
109 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
115 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
128 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
136 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
142 … after an interval where the front-end delivered no uops for a period of 2 cycles which was not in…
155 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
168 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
176 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
182 …r an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was n…
195 …r an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was n…
208 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
216 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
222 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
235 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
248 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
261 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
269 …tions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this…
289 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
294 …"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache mis…
299 …"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts…
308 …"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Count…
317 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
332 …"PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queu…
343 …"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue …
354 …"PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode …
365 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
370 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
376 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
381 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
386 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
391 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
397 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
402         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
407 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
412 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while …
418 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
423 …en uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (I…
429 …ch uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (I…
434 …"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while …
439 …iption": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (I…
456 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (M…
461 …he total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops wil…
471 …Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs…
482 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
504 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
515         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
526         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",