1959826caSMatt Macy[ 2959826caSMatt Macy { 3*18054d02SAlexander Motin "BriefDescription": "ITLB misses", 4959826caSMatt Macy "CollectPEBSRecord": "1", 5959826caSMatt Macy "Counter": "0,1,2,3", 6959826caSMatt Macy "EventCode": "0x81", 7959826caSMatt Macy "EventName": "ITLB.MISS", 8*18054d02SAlexander Motin "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", 9959826caSMatt Macy "SampleAfterValue": "200003", 10*18054d02SAlexander Motin "UMask": "0x4" 11959826caSMatt Macy }, 12959826caSMatt Macy { 1392b14858SMatt Macy "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)", 14*18054d02SAlexander Motin "CollectPEBSRecord": "2", 15*18054d02SAlexander Motin "Counter": "0,1,2,3", 16*18054d02SAlexander Motin "Data_LA": "1", 17*18054d02SAlexander Motin "EventCode": "0xD0", 18*18054d02SAlexander Motin "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", 19*18054d02SAlexander Motin "PEBS": "2", 20*18054d02SAlexander Motin "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", 21*18054d02SAlexander Motin "SampleAfterValue": "200003", 22*18054d02SAlexander Motin "UMask": "0x13" 23*18054d02SAlexander Motin }, 24*18054d02SAlexander Motin { 25*18054d02SAlexander Motin "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)", 26*18054d02SAlexander Motin "CollectPEBSRecord": "2", 27*18054d02SAlexander Motin "Counter": "0,1,2,3", 28*18054d02SAlexander Motin "Data_LA": "1", 29*18054d02SAlexander Motin "EventCode": "0xD0", 30*18054d02SAlexander Motin "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 31*18054d02SAlexander Motin "PEBS": "2", 32*18054d02SAlexander Motin "PublicDescription": "Counts load uops retired that caused a DTLB miss.", 33*18054d02SAlexander Motin "SampleAfterValue": "200003", 34*18054d02SAlexander Motin "UMask": "0x11" 35*18054d02SAlexander Motin }, 36*18054d02SAlexander Motin { 37*18054d02SAlexander Motin "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)", 38*18054d02SAlexander Motin "CollectPEBSRecord": "2", 39*18054d02SAlexander Motin "Counter": "0,1,2,3", 40*18054d02SAlexander Motin "Data_LA": "1", 41*18054d02SAlexander Motin "EventCode": "0xD0", 42*18054d02SAlexander Motin "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", 43*18054d02SAlexander Motin "PEBS": "2", 44*18054d02SAlexander Motin "PublicDescription": "Counts store uops retired that caused a DTLB miss.", 45*18054d02SAlexander Motin "SampleAfterValue": "200003", 46*18054d02SAlexander Motin "UMask": "0x12" 47*18054d02SAlexander Motin }, 48*18054d02SAlexander Motin { 49*18054d02SAlexander Motin "BriefDescription": "Duration of page-walks in cycles", 50*18054d02SAlexander Motin "CollectPEBSRecord": "1", 51*18054d02SAlexander Motin "Counter": "0,1,2,3", 52*18054d02SAlexander Motin "EventCode": "0x05", 53*18054d02SAlexander Motin "EventName": "PAGE_WALKS.CYCLES", 54*18054d02SAlexander Motin "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.", 55*18054d02SAlexander Motin "SampleAfterValue": "200003", 56*18054d02SAlexander Motin "UMask": "0x3" 57*18054d02SAlexander Motin }, 58*18054d02SAlexander Motin { 59*18054d02SAlexander Motin "BriefDescription": "Duration of D-side page-walks in cycles", 60*18054d02SAlexander Motin "CollectPEBSRecord": "1", 61*18054d02SAlexander Motin "Counter": "0,1,2,3", 62*18054d02SAlexander Motin "EventCode": "0x05", 63*18054d02SAlexander Motin "EventName": "PAGE_WALKS.D_SIDE_CYCLES", 64*18054d02SAlexander Motin "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.", 65*18054d02SAlexander Motin "SampleAfterValue": "200003", 66*18054d02SAlexander Motin "UMask": "0x1" 67*18054d02SAlexander Motin }, 68*18054d02SAlexander Motin { 69*18054d02SAlexander Motin "BriefDescription": "Duration of I-side pagewalks in cycles", 70*18054d02SAlexander Motin "CollectPEBSRecord": "1", 71*18054d02SAlexander Motin "Counter": "0,1,2,3", 72*18054d02SAlexander Motin "EventCode": "0x05", 73*18054d02SAlexander Motin "EventName": "PAGE_WALKS.I_SIDE_CYCLES", 74*18054d02SAlexander Motin "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.", 75*18054d02SAlexander Motin "SampleAfterValue": "200003", 76*18054d02SAlexander Motin "UMask": "0x2" 77959826caSMatt Macy } 78959826caSMatt Macy]