| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
13 The Mediatek infracfg controller provides various clocks and reset outputs
15 and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
17 <dt-bindings/reset/mediatek,mt*-infracfg.h>.
24 - mediatek,mt2701-infracfg
25 - mediatek,mt2712-infracfg
26 - mediatek,mt6735-infracfg
27 - mediatek,mt6765-infracfg
28 - mediatek,mt6795-infracfg
30 - mediatek,mt6797-infracfg
[all …]
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| H A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /linux/drivers/soc/mediatek/ |
| H A D | mtk-infracfg.c | 10 #include <linux/soc/mediatek/infracfg.h>
18 * @infracfg: The infracfg regmap
28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
49 * @infracfg: The infracfg regmap
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
[all …]
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8365.dtsi | 301 infracfg: syscon@10001000 { label
302 compatible = "mediatek,mt8365-infracfg", "syscon";
340 mediatek,infracfg = <&infracfg>;
341 mediatek,infracfg-nao = <&infracfg_nao>;
357 mediatek,infracfg = <&infracfg>;
375 clocks = <&infracfg CLK_IFR_APU_AXI>,
387 mediatek,infracfg = <&infracfg>;
398 mediatek,infracfg = <&infracfg>;
406 mediatek,infracfg = <&infracfg>;
412 <&infracfg CLK_IFR_AUDIO>,
[all …]
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| H A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
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| H A D | mt8192.dtsi | 459 infracfg: syscon@10001000 { label
460 compatible = "mediatek,mt8192-infracfg", "syscon";
512 <&infracfg CLK_INFRA_AUDIO_26M_B>,
513 <&infracfg CLK_INFRA_AUDIO>;
515 mediatek,infracfg = <&infracfg>;
521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
523 mediatek,infracfg = <&infracfg>;
538 mediatek,infracfg = <&infracfg>;
579 mediatek,infracfg = <&infracfg>;
593 mediatek,infracfg = <&infracfg>;
[all …]
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| H A D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
363 infracfg: clock-controller@10001000 { label
364 compatible = "mediatek,mt8173-infracfg", "syscon";
489 mediatek,infracfg = <&infracfg>;
523 mediatek,infracfg = <&infracfg>;
541 clocks = <&infracfg CLK_INFRA_CLK_13M>,
550 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
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| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
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| H A D | mt2712e.dtsi | 252 infracfg: clock-controller@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
332 mediatek,infracfg = <&infracfg>;
348 clocks = <&infracfg CLK_INFRA_M4U>;
350 mediatek,infracfg = <&infracfg>;
663 <&infracfg CLK_INFRA_AO_SPI0>;
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8192-afe-pcm.yaml | 34 mediatek,infracfg:
36 description: The phandle of the mediatek infracfg controller
67 - mediatek,infracfg
89 mediatek,infracfg = <&infracfg>;
95 <&infracfg CLK_INFRA_AUDIO>,
96 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| H A D | mt8186-afe-pcm.yaml | 36 mediatek,infracfg:
38 description: The phandle of the mediatek infracfg controller
106 - mediatek,infracfg
125 mediatek,infracfg = <&infracfg>;
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| H A D | mediatek,mt8188-afe.yaml | 38 mediatek,infracfg:
40 description: The phandle of the mediatek infracfg controller
167 - mediatek,infracfg
187 mediatek,infracfg = <&infracfg_ao>;
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| H A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-infracfg.c | 12 #include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
13 #include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
90 { .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
99 .name = "clk-mt6735-infracfg",
106 MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
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| H A D | clk-mt8173-infracfg.c | 74 { .compatible = "mediatek,mt8173-infracfg" },
95 CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
155 .name = "clk-mt8173-infracfg",
163 MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver");
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| H A D | Makefile | 5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
26 obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
55 clk-mt7622-infracfg.o
64 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
68 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
72 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
82 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
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| H A D | clk-mt7622-infracfg.c | 55 { .compatible = "mediatek,mt7622-infracfg" },
117 .name = "clk-mt7622-infracfg",
125 MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
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| H A D | clk-mt6795-infracfg.c | 81 { .compatible = "mediatek,mt6795-infracfg" },
143 .name = "clk-mt6795-infracfg",
151 MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 323 clocks = <&infracfg 44>,
324 <&infracfg 40>,
325 <&infracfg 43>,
326 <&infracfg 97>,
327 <&infracfg 99>,
328 <&infracfg 111>;
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
133 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
473 mediatek,infracfg = <&infracfg>;
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| H A D | mt8135.dtsi | 133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
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| H A D | mt2701.dtsi | 132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
192 clocks = <&infracfg CLK_INFRA_SMI>,
194 <&infracfg CLK_INFRA_SMI>;
222 clocks = <&infracfg CLK_INFRA_M4U>;
434 clocks = <&infracfg CLK_INFRA_AUDIO>,
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| H A D | mt7623n.dtsi | 108 clocks = <&infracfg CLK_INFRA_M4U>;
132 clocks = <&infracfg CLK_INFRA_SMI>,
134 <&infracfg CLK_INFRA_SMI>;
259 clocks = <&infracfg CLK_INFRA_CEC>;
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mediatek,net.yaml | 86 mediatek,infracfg:
171 mediatek,infracfg: false
205 mediatek,infracfg: false
246 mediatek,infracfg: false
341 mediatek,infracfg: false
382 mediatek,infracfg: false
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | mediatek,ufs-phy.yaml | 63 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
64 <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
|