| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
13 The Mediatek infracfg controller provides various clocks and reset outputs
15 and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
17 <dt-bindings/reset/mediatek,mt*-infracfg.h>.
24 - mediatek,mt2701-infracfg
25 - mediatek,mt2712-infracfg
26 - mediatek,mt6735-infracfg
27 - mediatek,mt6765-infracfg
28 - mediatek,mt6795-infracfg
30 - mediatek,mt6797-infracfg
[all …]
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| H A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /linux/drivers/soc/mediatek/ |
| H A D | mtk-infracfg.c | 10 #include <linux/soc/mediatek/infracfg.h>
18 * @infracfg: The infracfg regmap
28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
49 * @infracfg: The infracfg regmap
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
[all …]
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7988a.dtsi | 135 infracfg: clock-controller@10001000 { label
136 compatible = "mediatek,mt7988-infracfg", "syscon";
231 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
232 <&infracfg CLK_INFRA_66M_PWM_HCK>,
233 <&infracfg CLK_INFRA_66M_PWM_CK1>,
234 <&infracfg CLK_INFRA_66M_PWM_CK2>,
235 <&infracfg CLK_INFRA_66M_PWM_CK3>,
236 <&infracfg CLK_INFRA_66M_PWM_CK4>,
237 <&infracfg CLK_INFRA_66M_PWM_CK5>,
238 <&infracfg CLK_INFRA_66M_PWM_CK6>,
[all …]
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| H A D | mt7981b.dtsi | 60 infracfg: clock-controller@10001000 { label
61 compatible = "mediatek,mt7981-infracfg", "syscon";
88 clocks = <&infracfg CLK_INFRA_PWM_STA>,
89 <&infracfg CLK_INFRA_PWM_HCK>,
90 <&infracfg CLK_INFRA_PWM1_CK>,
91 <&infracfg CLK_INFRA_PWM2_CK>,
92 <&infracfg CLK_INFRA_PWM3_CK>;
102 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
103 <&infracfg CLK_INFRA_UART0_CK>;
113 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
[all …]
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| H A D | mt7986a.dtsi | 143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
[all …]
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| H A D | mt8365.dtsi | 301 infracfg: syscon@10001000 { label
302 compatible = "mediatek,mt8365-infracfg", "syscon";
340 mediatek,infracfg = <&infracfg>;
341 mediatek,infracfg-nao = <&infracfg_nao>;
357 mediatek,infracfg = <&infracfg>;
375 clocks = <&infracfg CLK_IFR_APU_AXI>,
387 mediatek,infracfg = <&infracfg>;
398 mediatek,infracfg = <&infracfg>;
406 mediatek,infracfg = <&infracfg>;
412 <&infracfg CLK_IFR_AUDIO>,
[all …]
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| H A D | mt8183.dtsi | 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
[all …]
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| H A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
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| H A D | mt8192.dtsi | 459 infracfg: syscon@10001000 { label
460 compatible = "mediatek,mt8192-infracfg", "syscon";
512 <&infracfg CLK_INFRA_AUDIO_26M_B>,
513 <&infracfg CLK_INFRA_AUDIO>;
515 mediatek,infracfg = <&infracfg>;
521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
523 mediatek,infracfg = <&infracfg>;
538 mediatek,infracfg = <&infracfg>;
579 mediatek,infracfg = <&infracfg>;
593 mediatek,infracfg = <&infracfg>;
[all …]
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| H A D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: clock-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
481 mediatek,infracfg = <&infracfg>;
515 mediatek,infracfg = <&infracfg>;
533 clocks = <&infracfg CLK_INFRA_CLK_13M>,
542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
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| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg:
32 description: The phandle of the mediatek infracfg controller
63 - mediatek,infracfg
85 mediatek,infracfg = <&infracfg>;
91 <&infracfg CLK_INFRA_AUDIO>,
92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| H A D | mt8186-afe-pcm.yaml | 32 mediatek,infracfg:
34 description: The phandle of the mediatek infracfg controller
102 - mediatek,infracfg
121 mediatek,infracfg = <&infracfg>;
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| H A D | mediatek,mt8188-afe.yaml | 38 mediatek,infracfg:
40 description: The phandle of the mediatek infracfg controller
167 - mediatek,infracfg
187 mediatek,infracfg = <&infracfg_ao>;
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| H A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
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| /linux/Documentation/devicetree/bindings/power/ |
| H A D | mediatek,power-controller.yaml | 123 mediatek,infracfg:
125 description: phandle to the device containing the INFRACFG register range.
127 mediatek,infracfg-nao:
129 description: phandle to the device containing the INFRACFG-NAO register range.
187 mediatek,infracfg = <&infracfg>;
221 mediatek,infracfg = <&infracfg>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-infracfg.c | 12 #include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
13 #include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
90 { .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
99 .name = "clk-mt6735-infracfg",
106 MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
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| H A D | Makefile | 5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
26 obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
55 clk-mt7622-infracfg.o
64 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
68 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
72 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
82 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
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| H A D | clk-mt8173-infracfg.c | 74 { .compatible = "mediatek,mt8173-infracfg" },
95 CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
155 .name = "clk-mt8173-infracfg",
163 MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver");
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| H A D | clk-mt7622-infracfg.c | 55 { .compatible = "mediatek,mt7622-infracfg" },
117 .name = "clk-mt7622-infracfg",
125 MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | mediatek,iommu.yaml | 110 mediatek,infracfg:
112 description: The phandle to the mediatek infracfg syscon
202 - mediatek,infracfg
228 clocks = <&infracfg CLK_INFRA_M4U>;
230 mediatek,infracfg = <&infracfg>;
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| /linux/drivers/pmdomain/mediatek/ |
| H A D | mtk-pm-domains.c | 17 #include <linux/soc/mediatek/infracfg.h>
51 struct regmap *infracfg; member
131 return pd->infracfg; in scpsys_bus_protect_get_regmap()
399 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); in scpsys_add_one_domain()
400 if (IS_ERR(pd->infracfg)) in scpsys_add_one_domain()
401 return dev_err_cast_probe(scpsys->dev, pd->infracfg, in scpsys_add_one_domain()
402 "%pOF: failed to get infracfg regmap\n", in scpsys_add_one_domain()
416 pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao"); in scpsys_add_one_domain()
419 "%pOF: failed to get infracfg-nao regmap\n", in scpsys_add_one_domain()
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mediatek,net.yaml | 70 mediatek,infracfg:
149 mediatek,infracfg: false
178 mediatek,infracfg: false
213 mediatek,infracfg: false
299 mediatek,infracfg: false
337 mediatek,infracfg: false
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
133 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
473 mediatek,infracfg = <&infracfg>;
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