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/linux/arch/arm64/boot/dts/freescale/
H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
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H A Dimx95-tqma9596sa-mb-smarc-2.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 #include "imx95-tqma9596sa.dtsi"
14 model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2";
15 compatible = "tq,imx95-tqma9596sa-mb-smarc-2", "tq,imx95-tqma9596sa", "fsl,imx95";
45 stdout-path = &lpuart7;
48 backlight_lvds0: backlight-lvds0 {
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H A Dimx95-19x19-evk-sof.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx95-19x19-evk.dts"
11 sof_cpu: cm7-cpu@80000000 {
12 compatible = "fsl,imx95-cm7-sof";
14 reg-names = "sram";
15 memory-region = <&adma_res>;
16 memory-region-names = "dma";
18 mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
22 remote-endpoint = <&wm8962_ep>;
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H A Dimx95-phycore-fpsc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/net/ti-dp83867.h>
7 #include "imx95.dtsi"
10 model = "PHYTEC phyCORE-i.MX95 FPSC";
11 compatible = "phytec,imx95-phycore-fpsc", "fsl,imx95";
29 reg_nvcc_aon: regulator-nvcc-aon {
30 compatible = "regulator-fixed";
31 regulator-always-on;
32 regulator-boot-on;
33 regulator-max-microvolt = <1800000>;
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H A Dimx95-19x19-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/usb/pd.h>
10 #include "imx95.dtsi"
15 #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
16 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
17 #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
18 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
19 #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
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/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
30 The clock consumer should specify the desired clock by having the clock
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/linux/drivers/clk/imx/
H A Dclk-imx95-blk-ctl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/clock/nxp,imx94-clock.h>
7 #include <dt-bindings/clock/nxp,imx95-clock.h>
9 #include <linux/clk-provider.h>
37 /* clock gate register */
352 struct device *dev = &pdev->dev; in imx95_bc_probe()
361 return -ENOMEM; in imx95_bc_probe()
362 bc->dev = dev; in imx95_bc_probe()
363 dev_set_drvdata(&pdev->dev, bc); in imx95_bc_probe()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for NXP i.MX SoC family.
4 tristate "IMX clock"
67 tristate "IMX8MM CCM Clock Driver"
71 Build the driver for i.MX8MM CCM Clock Driver
74 tristate "IMX8MN CCM Clock Driver"
78 Build the driver for i.MX8MN CCM Clock Driver
81 tristate "IMX8MP CCM Clock Driver"
86 Build the driver for i.MX8MP CCM Clock Driver
89 tristate "IMX8MQ CCM Clock Driver"
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
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/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
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/linux/Documentation/devicetree/bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
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H A Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Li Jun <jun.li@nxp.com>
16 - items:
17 - const: fsl,imx95-dwc3
18 - const: fsl,imx8mp-dwc3
19 - const: fsl,imx8mp-dwc3
23 - description: Address and length of the register set for HSIO Block Control
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/linux/Documentation/devicetree/bindings/i3c/
H A Dsilvaco,i3c-master.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Culhane <conor.culhane@silvaco.com>
15 - enum:
16 - nuvoton,npcm845-i3c
17 - silvaco,i3c-master-v1
18 - items:
19 - enum:
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/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
22 - enum:
23 - nxp,imx95-sysctr-timer
24 - nxp,sysctr-timer
25 - items:
26 - enum:
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,mqs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 - Chancel Liu <chancel.liu@nxp.com>
22 - fsl,imx6sx-mqs
23 - fsl,imx8qm-mqs
24 - fsl,imx8qxp-mqs
25 - fsl,imx93-mqs
26 - fsl,imx943-aonmix-mqs
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H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
29 - fsl,imx8mp-rpmsg-audio
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/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
16 - enum:
17 - fsl,imx95-flexcan
18 - fsl,imx93-flexcan
19 - fsl,imx8qm-flexcan
20 - fsl,imx8mp-flexcan
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-nxp-fspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
11 - Kuldeep Singh <singh.kuldeep87k@gmail.com>
14 - $ref: spi-controller.yaml#
19 - enum:
20 - nxp,imx8dxl-fspi
21 - nxp,imx8mm-fspi
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H A Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,imx8ulp-gpio
24 - const: fsl,vf610-gpio
25 - items:
26 - const: fsl,imx7ulp-gpio
27 - const: fsl,vf610-gpio
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 This binding represents the on-chip eFuse OTP controller found on
20 - $ref: nvmem.yaml#
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/linux/sound/soc/fsl/
H A Dfsl_mqs.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
39 * struct fsl_mqs_soc_data - soc specific data
50 * @div_mask: clock divider mask
51 * @div_shift: clock divider bit shift
86 mqs_priv->soc->ctrl_off == reg) in fsl_mqs_sm_read()
87 return scmi_imx_misc_ctrl_get(mqs_priv->soc->sm_index, &num, val); in fsl_mqs_sm_read()
89 return -EINVAL; in fsl_mqs_sm_read()
97 mqs_priv->soc->ctrl_off == reg) in fsl_mqs_sm_write()
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/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
42 * 32bit counters monitor counter-specific events in addition to counting reference events
74 * respecitively to counter 2-5.
113 .identifier = "imx95",
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
124 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
128 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
129 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
130 { .compatible = "fsl,imx94-ddr-pmu", .data = &imx94_devtype_data },
131 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
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/linux/drivers/clocksource/
H A Dtimer-imx-sysctr.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2017-2019 NXP
9 #include "timer-of.h"
36 struct sysctr_private *priv = to->private_data; in sysctr_timer_enable()
39 writel(enable ? priv->cmpcr | SYS_CTR_EN : priv->cmpcr, base + CMPCR); in sysctr_timer_enable()
55 struct sysctr_private *priv = to->private_data; in sysctr_read_counter()
60 cnt_hi = readl_relaxed(base + priv->hi_off); in sysctr_read_counter()
61 cnt_lo = readl_relaxed(base + priv->lo_off); in sysctr_read_counter()
62 tmp_hi = readl_relaxed(base + priv->hi_off); in sysctr_read_counter()
111 evt->event_handler(evt); in sysctr_timer_interrupt()
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/linux/drivers/pci/controller/dwc/
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
93 IMX95, enumerator
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
183 /* PCIe Port Logic registers (memory-mapped) */
196 /* PHY registers (not memory-mapped) */
233 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
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