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/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,imx95-blk-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
15 - enum:
16 - nxp,imx95-camera-csr
17 - nxp,imx95-display-csr
18 - nxp,imx95-hsio-blk-ctl
19 - nxp,imx95-lvds-csr
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H A Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
30 The clock consumer should specify the desired clock by having the clock
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
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/linux/drivers/clk/imx/
H A Dclk-imx95-blk-ctl.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
8 #include <linux/clk-provider.h>
36 /* clock gate register */
301 struct device *dev = &pdev->dev; in imx95_bc_probe()
311 return -ENOMEM; in imx95_bc_probe()
312 bc->dev = dev; in imx95_bc_probe()
313 dev_set_drvdata(&pdev->dev, bc); in imx95_bc_probe()
315 spin_lock_init(&bc->lock); in imx95_bc_probe()
321 bc->base = base; in imx95_bc_probe()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for NXP i.MX SoC family.
4 tristate "IMX clock"
67 tristate "IMX8MM CCM Clock Driver"
71 Build the driver for i.MX8MM CCM Clock Driver
74 tristate "IMX8MN CCM Clock Driver"
78 Build the driver for i.MX8MN CCM Clock Driver
81 tristate "IMX8MP CCM Clock Driver"
86 Build the driver for i.MX8MP CCM Clock Driver
89 tristate "IMX8MQ CCM Clock Driver"
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
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/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
22 - nxp,imx95-sysctr-timer
23 - nxp,sysctr-timer
34 clock-names:
37 nxp,no-divider:
42 - compatible
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-imx-lpi2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-lpi2c
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/linux/Documentation/devicetree/bindings/serial/
H A Dfsl-lpuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fugang Duan <fugang.duan@nxp.com>
13 - $ref: rs485.yaml#
14 - $ref: serial.yaml#
19 - enum:
20 - fsl,vf610-lpuart
21 - fsl,ls1021a-lpuart
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
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H A Dspi-nxp-fspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
11 - Kuldeep Singh <singh.kuldeep87k@gmail.com>
14 - $ref: spi-controller.yaml#
19 - enum:
20 - nxp,imx8dxl-fspi
21 - nxp,imx8mm-fspi
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,imx8ulp-gpio
24 - const: fsl,vf610-gpio
25 - items:
26 - const: fsl,imx7ulp-gpio
27 - const: fsl,vf610-gpio
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 This binding represents the on-chip eFuse OTP controller found on
20 - $ref: nvmem.yaml#
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
29 - fsl,imx8mp-rpmsg-audio
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H A Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
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/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
22 - fsl,imx8qm-flexcan
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/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
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/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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/linux/drivers/clocksource/
H A Dtimer-imx-sysctr.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2017-2019 NXP
9 #include "timer-of.h"
36 struct sysctr_private *priv = to->private_data; in sysctr_timer_enable()
39 writel(enable ? priv->cmpcr | SYS_CTR_EN : priv->cmpcr, base + CMPCR); in sysctr_timer_enable()
55 struct sysctr_private *priv = to->private_data; in sysctr_read_counter()
60 cnt_hi = readl_relaxed(base + priv->hi_off); in sysctr_read_counter()
61 cnt_lo = readl_relaxed(base + priv->lo_off); in sysctr_read_counter()
62 tmp_hi = readl_relaxed(base + priv->hi_off); in sysctr_read_counter()
111 evt->event_handler(evt); in sysctr_timer_interrupt()
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/linux/sound/soc/fsl/
H A Dfsl_rpmsg.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2018-2021 NXP
5 #include <linux/clk-provider.h>
18 #include "imx-pcm.h"
44 struct clk *p = rpmsg->mclk, *pll = NULL, *npll = NULL; in fsl_rpmsg_hw_params()
49 while (p && rpmsg->pll8k && rpmsg->pll11k) { in fsl_rpmsg_hw_params()
52 if (clk_is_match(pp, rpmsg->pll8k) || in fsl_rpmsg_hw_params()
53 clk_is_match(pp, rpmsg->pll11k)) { in fsl_rpmsg_hw_params()
62 npll = (do_div(rate, 8000) ? rpmsg->pll11k : rpmsg->pll8k); in fsl_rpmsg_hw_params()
66 dev_warn(dai->dev, "failed to set parent %s: %d\n", in fsl_rpmsg_hw_params()
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H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); in fsl_sai_get_pins_state()
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H A Dfsl_xcvr.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
117 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
151 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
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/linux/drivers/mailbox/
H A Dimx-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
29 /* TX0/RX0/RXDB[0-3] */
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
151 iowrite32(val, priv->base + offs); in imx_mu_write()
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/linux/drivers/dma/
H A Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/dma/fsl-edma.h>
20 #include <linux/dma-mapping.h>
25 #include "fsl-edma-common.h"
31 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
38 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
40 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
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/linux/drivers/net/can/flexcan/
H A Dflexcan-core.c1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 #include <dt-bindings/firmware/imx/rsrc.h>
219 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
222 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
223 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
224 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
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