Lines Matching +full:imx95 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/clock/nxp,imx94-clock.h>
7 #include <dt-bindings/clock/nxp,imx95-clock.h>
9 #include <linux/clk-provider.h>
37 /* clock gate register */
351 struct device *dev = &pdev->dev;
361 return -ENOMEM;
362 bc->dev = dev;
363 dev_set_drvdata(&pdev->dev, bc);
365 spin_lock_init(&bc->lock);
371 bc->base = base;
372 bc->clk_apb = devm_clk_get(dev, NULL);
373 if (IS_ERR(bc->clk_apb))
374 return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");
376 ret = clk_prepare_enable(bc->clk_apb);
378 dev_err(dev, "failed to enable apb clock: %d\n", ret);
386 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->num_clks),
389 return -ENOMEM;
391 if (bc_data->rpm_enabled) {
392 devm_pm_runtime_enable(&pdev->dev);
393 pm_runtime_resume_and_get(&pdev->dev);
396 clk_hw_data->num = bc_data->num_clks;
397 hws = clk_hw_data->hws;
399 for (i = 0; i < bc_data->num_clks; i++) {
400 const struct imx95_blk_ctl_clk_dev_data *data = &bc_data->clk_dev_data[i];
401 void __iomem *reg = base + data->reg;
403 if (data->type == CLK_MUX) {
404 hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
405 data->num_parents, data->flags, reg,
406 data->bit_idx, data->bit_width,
407 data->flags2, &bc->lock);
408 } else if (data->type == CLK_DIVIDER) {
409 hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],
410 data->flags, reg, data->bit_idx,
411 data->bit_width, data->flags2, &bc->lock);
413 hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],
414 data->flags, reg, data->bit_idx,
415 data->flags2, &bc->lock);
419 dev_err(dev, "failed to register: %s:%d\n", data->name, ret);
424 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_hw_data);
430 of_clk_del_provider(dev->of_node);
434 if (pm_runtime_enabled(bc->dev)) {
435 pm_runtime_put_sync(&pdev->dev);
436 clk_disable_unprepare(bc->clk_apb);
442 for (i = 0; i < bc_data->num_clks; i++) {
456 clk_disable_unprepare(bc->clk_apb);
464 return clk_prepare_enable(bc->clk_apb);
479 if (bc_data->rpm_enabled) {
480 ret = pm_runtime_get_sync(bc->dev);
482 pm_runtime_put_noidle(bc->dev);
487 bc->clk_reg_restore = readl(bc->base + bc_data->clk_reg_offset);
501 writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset);
503 if (bc_data->rpm_enabled)
504 pm_runtime_put(bc->dev);
516 { .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
517 { .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
518 { .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
519 { .compatible = "nxp,imx95-display-master-csr", },
520 { .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },
521 { .compatible = "nxp,imx95-lvds-csr", .data = &imx95_lvds_csr_dev_data },
522 { .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
523 { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
524 { .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
532 .name = "imx95-blk-ctl",