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/linux/Documentation/devicetree/bindings/clock/
H A Dimx93-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 Clock Control Module
10 - Peng Fan <peng.fan@nxp.com>
13 i.MX93 clock control module is an integrated clock controller, which
14 includes clock generator, clock gate and supplies to all modules.
19 - fsl,imx91-ccm
20 - fsl,imx93-ccm
[all …]
H A Dfsl,imx93-anatop.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,imx93-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 ANATOP Clock Module
10 - Peng Fan <peng.fan@nxp.com>
13 NXP i.MX93 ANATOP module which contains PLL and OSC to Clock Controller
19 - const: fsl,imx93-anatop
24 '#clock-cells':
28 - compatible
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
22 const: fsl,imx93-mipi-dsi
26 - description: apb clock
27 - description: pixel clock
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx93-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
17 - Deals with all global system reset sources from other modules,
19 - Responsible for power gating of MIXs (Slices) and their memory
25 - const: fsl,imx93-src
26 - const: syscon
33 '#address-cells':
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/linux/Documentation/devicetree/bindings/display/
H A Dfsl,lcdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Stefan Agner <stefan@agner.ch>
19 - enum:
20 - fsl,imx23-lcdif
21 - fsl,imx28-lcdif
22 - fsl,imx6sx-lcdif
23 - fsl,imx8mp-lcdif
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
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/linux/Documentation/devicetree/bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
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/linux/drivers/clk/imx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for NXP i.MX SoC family.
4 tristate "IMX clock"
67 tristate "IMX8MM CCM Clock Driver"
71 Build the driver for i.MX8MM CCM Clock Driver
74 tristate "IMX8MN CCM Clock Driver"
78 Build the driver for i.MX8MN CCM Clock Driver
81 tristate "IMX8MP CCM Clock Driver"
86 Build the driver for i.MX8MP CCM Clock Driver
89 tristate "IMX8MQ CCM Clock Driver"
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-tqma9352.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include "imx93.dtsi"
11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
12 compatible = "tq,imx93-tqma9352", "fsl,imx93";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
26 compatible = "shared-dma-pool";
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H A Dimx93-9x9-qsb.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include "imx93.dtsi"
13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";
15 bt_sco_codec: bt-sco-codec {
16 #sound-dai-cells = <1>;
17 compatible = "linux,bt-sco";
39 stdout-path = &lpuart1;
42 reserved-memory {
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-nxp-fspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
11 - Kuldeep Singh <singh.kuldeep87k@gmail.com>
14 - $ref: spi-controller.yaml#
19 - enum:
20 - nxp,imx8dxl-fspi
21 - nxp,imx8mm-fspi
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H A Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,imx8ulp-gpio
24 - const: fsl,vf610-gpio
25 - items:
26 - const: fsl,imx7ulp-gpio
27 - const: fsl,vf610-gpio
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 This binding represents the on-chip eFuse OTP controller found on
21 - $ref: nvmem.yaml#
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
16 - enum:
17 - fsl,imx95-flexcan
18 - fsl,imx93-flexcan
19 - fsl,imx8qm-flexcan
20 - fsl,imx8mp-flexcan
[all …]
/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
42 * 32bit counters monitor counter-specific events in addition to counting reference events
74 * respecitively to counter 2-5.
103 .identifier = "imx93",
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
124 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
128 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
129 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
130 { .compatible = "fsl,imx94-ddr-pmu", .data = &imx94_devtype_data },
131 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
[all …]
/linux/sound/soc/fsl/
H A Dfsl_mqs.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
39 * struct fsl_mqs_soc_data - soc specific data
50 * @div_mask: clock divider mask
51 * @div_shift: clock divider bit shift
86 mqs_priv->soc->ctrl_off == reg) in fsl_mqs_sm_read()
87 return scmi_imx_misc_ctrl_get(mqs_priv->soc->sm_index, &num, val); in fsl_mqs_sm_read()
89 return -EINVAL; in fsl_mqs_sm_read()
97 mqs_priv->soc->ctrl_off == reg) in fsl_mqs_sm_write()
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H A Dfsl_rpmsg.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2018-2021 NXP
5 #include <linux/clk-provider.h>
18 #include "imx-pcm.h"
46 struct clk *p = rpmsg->mclk, *pll = NULL, *npll = NULL; in fsl_rpmsg_hw_params()
51 while (p && rpmsg->pll8k && rpmsg->pll11k) { in fsl_rpmsg_hw_params()
54 if (clk_is_match(pp, rpmsg->pll8k) || in fsl_rpmsg_hw_params()
55 clk_is_match(pp, rpmsg->pll11k)) { in fsl_rpmsg_hw_params()
64 npll = (do_div(rate, 8000) ? rpmsg->pll11k : rpmsg->pll8k); in fsl_rpmsg_hw_params()
68 dev_warn(dai->dev, "failed to set parent %s: %d\n", in fsl_rpmsg_hw_params()
[all …]
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #include "imx-pcm.h"
91 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
105 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
112 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
115 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
119 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
123 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); in fsl_sai_get_pins_state()
[all …]
H A Dfsl_micfil.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
19 #include <linux/dma/imx-dma.h>
35 /* clock source ids */
147 .fifo_offset = -4,
153 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
154 { .compatible = "fsl,imx8mp-micfi
[all...]
/linux/drivers/dma/
H A Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/dma/fsl-edma.h>
20 #include <linux/dma-mapping.h>
25 #include "fsl-edma-common.h"
31 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
38 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
40 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
[all …]
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/media-bus-format.h>
17 #include <linux/phy/phy-mipi-dphy.h>
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2))
44 #define N(x) FIELD_PREP(N_MASK, ((x) - 1))
121 /* DPHY Databook Table 3-13 Charge-pump Programmability */
136 /* DPHY Databook Table 5-7 Frequency Ranges and Defaults */
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
209 dev_err(dsi->dev, "failed to write 0x%08x to pll reg 0x%x: %d\n", in dphy_pll_write()
224 struct device *dev = dsi->dev; in dphy_pll_get_configure_from_opts()
[all …]
/linux/drivers/spi/
H A Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/dma-mapping.h>
23 #include <linux/dma/imx-dma.h>
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
160 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
161 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
162 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
170 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
172 if (fsl_lpspi->rx_buf) { \
173 *(type *)fsl_lpspi->rx_buf = val; \
[all …]
/linux/drivers/iio/adc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 called 88pm886-gpadc.
26 bool "ST-Ericsson AB8500 GPADC driver"
98 high speed, low noise, low distortion, 20-bit, Easy Drive,
99 successive approximation register (SAR) analog-to-digital
114 Say yes here to build support for Analog Devices AD4130-8 SPI analog
133 tristate "Analog Device AD4170-4 ADC Driver"
141 Say yes here to build support for Analog Devices AD4170-4 SPI analog
145 called ad4170-4.
185 Say yes here to build support for Analog Devices AD7091R-5 ADC.
[all …]

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