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Searched +full:imx51 +full:- +full:src (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Dfsl,imx-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philipp Zabel <p.zabel@pengutronix.de>
15 nodes should specify the reset line on the SRC in their resets
16 property, containing a phandle to the SRC device node and a
31 - const: fsl,imx51-src
32 - items:
33 - enum:
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/linux/arch/arm/mach-imx/
H A Dsrc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/reset-controller.h>
61 return -EINVAL; in imx_src_reset_module()
74 return -ETIME; in imx_src_reset_module()
132 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); in imx_enable_cpu()
137 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); in imx_enable_cpu()
140 val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); in imx_enable_cpu()
170 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src"); in imx_src_init()
193 np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src"); in imx7_src_init()
201 np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); in imx7_src_init()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y := cpu.o system.o irq-common.o
4 obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
6 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
8 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
9 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
11 imx5-pm-$(CONFIG_PM) += pm-imx5.o
12 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)
14 obj-$(CONFIG_MXC_TZIC) += tzic.o
15 obj-$(CONFIG_MXC_AVIC) += avic.o
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
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H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
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/linux/drivers/gpu/ipu-v3/
H A Dipu-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
193 return -EINVAL; in ipu_rot_mode_to_degrees()
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
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/linux/drivers/mtd/nand/raw/
H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
28 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
29 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
30 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
31 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
32 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
33 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
34 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
35 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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