Lines Matching +full:imx51 +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
193 return -EINVAL; in ipu_rot_mode_to_degrees()
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
207 return ERR_PTR(-ENODEV); in ipu_idmac_get()
209 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
211 list_for_each_entry(channel, &ipu->channels, list) { in ipu_idmac_get()
212 if (channel->num == num) { in ipu_idmac_get()
213 channel = ERR_PTR(-EBUSY); in ipu_idmac_get()
220 channel = ERR_PTR(-ENOMEM); in ipu_idmac_get()
224 channel->num = num; in ipu_idmac_get()
225 channel->ipu = ipu; in ipu_idmac_get()
226 list_add(&channel->list, &ipu->channels); in ipu_idmac_get()
229 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
237 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put()
239 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
241 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
243 list_del(&channel->list); in ipu_idmac_put()
246 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
257 * only says these are read-only registers). This operation is required
261 * re-enabling the channels.
265 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer()
266 unsigned int chno = channel->num; in __ipu_idmac_reset_current_buffer()
274 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer()
278 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
280 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
282 reg |= idma_mask(channel->num); in ipu_idmac_set_double_buffer()
284 reg &= ~idma_mask(channel->num); in ipu_idmac_set_double_buffer()
285 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
289 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
319 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable()
339 return -EINVAL; in ipu_idmac_lock_enable()
347 if (bursts && ipu->ipu_type != IPUV3H) in ipu_idmac_lock_enable()
348 return -EINVAL; in ipu_idmac_lock_enable()
351 if (channel->num == idmac_lock_en_info[i].chnum) in ipu_idmac_lock_enable()
355 return -EINVAL; in ipu_idmac_lock_enable()
357 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
364 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
375 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
390 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
401 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
416 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
424 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer()
425 unsigned int chno = channel->num; in ipu_idmac_get_current_buffer()
433 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready()
437 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
440 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
443 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
446 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
449 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
451 return ((reg & idma_mask(channel->num)) != 0); in ipu_idmac_buffer_is_ready()
457 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer()
458 unsigned int chno = channel->num; in ipu_idmac_select_buffer()
461 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
469 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
475 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer()
476 unsigned int chno = channel->num; in ipu_idmac_clear_buffer()
479 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
497 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
503 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel()
507 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
509 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
510 val |= idma_mask(channel->num); in ipu_idmac_enable_channel()
511 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
513 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
527 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy()
531 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
532 idma_mask(channel->num)) { in ipu_idmac_wait_busy()
534 return -ETIMEDOUT; in ipu_idmac_wait_busy()
544 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel()
548 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
551 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
552 val &= ~idma_mask(channel->num); in ipu_idmac_disable_channel()
553 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
560 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
561 idma_mask(channel->num)) { in ipu_idmac_disable_channel()
562 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
563 IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_disable_channel()
566 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
567 idma_mask(channel->num)) { in ipu_idmac_disable_channel()
568 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
569 IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_disable_channel()
575 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
576 val &= ~idma_mask(channel->num); in ipu_idmac_disable_channel()
577 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
579 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
587 * a channel's priority. Refer to Table 36-8 Calculated priority value.
588 * The sub-module that is the sink or source for the channel must enable
593 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark()
597 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
599 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
601 val |= 1 << (channel->num % 32); in ipu_idmac_enable_watermark()
603 val &= ~(1 << (channel->num % 32)); in ipu_idmac_enable_watermark()
604 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
606 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
619 return -ETIME; in ipu_memory_reset()
638 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
647 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
659 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
674 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
689 struct fsu_link_reg_info src; member
695 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
700 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
705 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
710 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
716 static const struct fsu_link_info *find_fsu_link_info(int src, int sink) in find_fsu_link_info() argument
721 if (src == fsu_link_info[i].src.chno && in find_fsu_link_info()
740 return -EINVAL; in ipu_fsu_link()
742 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_link()
744 if (link->src.mask) { in ipu_fsu_link()
745 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_link()
746 src_reg &= ~link->src.mask; in ipu_fsu_link()
747 src_reg |= link->src.val; in ipu_fsu_link()
748 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_link()
751 if (link->sink.mask) { in ipu_fsu_link()
752 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_link()
753 sink_reg &= ~link->sink.mask; in ipu_fsu_link()
754 sink_reg |= link->sink.val; in ipu_fsu_link()
755 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_link()
758 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_link()
774 return -EINVAL; in ipu_fsu_unlink()
776 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_unlink()
778 if (link->src.mask) { in ipu_fsu_unlink()
779 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_unlink()
780 src_reg &= ~link->src.mask; in ipu_fsu_unlink()
781 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_unlink()
784 if (link->sink.mask) { in ipu_fsu_unlink()
785 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_unlink()
786 sink_reg &= ~link->sink.mask; in ipu_fsu_unlink()
787 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_unlink()
790 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_unlink()
796 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink) in ipu_idmac_link() argument
798 return ipu_fsu_link(src->ipu, src->num, sink->num); in ipu_idmac_link()
803 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink) in ipu_idmac_unlink() argument
805 return ipu_fsu_unlink(src->ipu, src->num, sink->num); in ipu_idmac_unlink()
874 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
875 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
876 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
877 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
888 struct device *dev = &pdev->dev; in ipu_submodules_init()
889 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
891 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
897 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
904 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
912 ipu_base + devtype->ic_ofs, in ipu_submodules_init()
913 ipu_base + devtype->tpm_ofs); in ipu_submodules_init()
919 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, in ipu_submodules_init()
933 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
940 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
947 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
948 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); in ipu_submodules_init()
955 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); in ipu_submodules_init()
961 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
968 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); in ipu_submodules_init()
999 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); in ipu_submodules_init()
1014 generic_handle_domain_irq(ipu->domain, in ipu_irq_handle()
1049 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
1051 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
1060 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
1091 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); in platform_device_unregister_children()
1105 .dma[1] = -EINVAL,
1107 .name = "imx-ipuv3-csi",
1112 .dma[1] = -EINVAL,
1114 .name = "imx-ipuv3-csi",
1123 .name = "imx-ipuv3-crtc",
1128 .dp = -EINVAL,
1130 .dma[1] = -EINVAL,
1132 .name = "imx-ipuv3-crtc",
1141 struct device *dev = ipu->dev; in ipu_add_client_devices()
1156 of_node = of_graph_get_port_by_id(dev->of_node, i); in ipu_add_client_devices()
1160 i, dev->of_node, in ipu_add_client_devices()
1165 pdev = platform_device_alloc(reg->name, id++); in ipu_add_client_devices()
1167 ret = -ENOMEM; in ipu_add_client_devices()
1172 pdev->dev.parent = dev; in ipu_add_client_devices()
1174 reg->pdata.of_node = of_node; in ipu_add_client_devices()
1175 ret = platform_device_add_data(pdev, ®->pdata, in ipu_add_client_devices()
1176 sizeof(reg->pdata)); in ipu_add_client_devices()
1210 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1212 if (!ipu->domain) { in ipu_irq_init()
1213 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1214 return -ENODEV; in ipu_irq_init()
1217 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1220 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1221 irq_domain_remove(ipu->domain); in ipu_irq_init()
1232 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1233 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1234 gc->unused = unused[i / 32]; in ipu_irq_init()
1235 ct = gc->chip_types; in ipu_irq_init()
1236 ct->chip.irq_ack = irq_gc_ack_set_bit; in ipu_irq_init()
1237 ct->chip.irq_mask = irq_gc_mask_clr_bit; in ipu_irq_init()
1238 ct->chip.irq_unmask = irq_gc_mask_set_bit; in ipu_irq_init()
1239 ct->regs.ack = IPU_INT_STAT(i / 32); in ipu_irq_init()
1240 ct->regs.mask = IPU_INT_CTRL(i / 32); in ipu_irq_init()
1243 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); in ipu_irq_init()
1244 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, in ipu_irq_init()
1254 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); in ipu_irq_exit()
1255 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); in ipu_irq_exit()
1260 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1265 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1272 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1274 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1276 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1278 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1280 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1282 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1284 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1286 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1288 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1290 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1292 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1294 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1296 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1298 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1301 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1308 struct device_node *np = pdev->dev.of_node; in ipu_probe()
1315 devtype = of_device_get_match_data(&pdev->dev); in ipu_probe()
1317 return -EINVAL; in ipu_probe()
1323 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", in ipu_probe()
1327 return -ENODEV; in ipu_probe()
1329 ipu_base = res->start; in ipu_probe()
1331 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1333 return -ENODEV; in ipu_probe()
1335 ipu->id = of_alias_get_id(np, "ipu"); in ipu_probe()
1336 if (ipu->id < 0) in ipu_probe()
1337 ipu->id = 0; in ipu_probe()
1339 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && in ipu_probe()
1341 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, in ipu_probe()
1342 "fsl,prg", ipu->id); in ipu_probe()
1343 if (!ipu->prg_priv) in ipu_probe()
1344 return -EPROBE_DEFER; in ipu_probe()
1347 ipu->devtype = devtype; in ipu_probe()
1348 ipu->ipu_type = devtype->type; in ipu_probe()
1350 spin_lock_init(&ipu->lock); in ipu_probe()
1351 mutex_init(&ipu->channel_lock); in ipu_probe()
1352 INIT_LIST_HEAD(&ipu->channels); in ipu_probe()
1354 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", in ipu_probe()
1355 ipu_base + devtype->cm_ofs); in ipu_probe()
1356 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", in ipu_probe()
1357 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); in ipu_probe()
1358 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", in ipu_probe()
1359 ipu_base + devtype->cpmem_ofs); in ipu_probe()
1360 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", in ipu_probe()
1361 ipu_base + devtype->csi0_ofs); in ipu_probe()
1362 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", in ipu_probe()
1363 ipu_base + devtype->csi1_ofs); in ipu_probe()
1364 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", in ipu_probe()
1365 ipu_base + devtype->ic_ofs); in ipu_probe()
1366 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", in ipu_probe()
1367 ipu_base + devtype->disp0_ofs); in ipu_probe()
1368 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", in ipu_probe()
1369 ipu_base + devtype->disp1_ofs); in ipu_probe()
1370 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", in ipu_probe()
1371 ipu_base + devtype->srm_ofs); in ipu_probe()
1372 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", in ipu_probe()
1373 ipu_base + devtype->tpm_ofs); in ipu_probe()
1374 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", in ipu_probe()
1375 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); in ipu_probe()
1376 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", in ipu_probe()
1377 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); in ipu_probe()
1378 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", in ipu_probe()
1379 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); in ipu_probe()
1380 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", in ipu_probe()
1381 ipu_base + devtype->vdi_ofs); in ipu_probe()
1383 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1384 ipu_base + devtype->cm_ofs, PAGE_SIZE); in ipu_probe()
1385 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1386 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, in ipu_probe()
1389 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1390 return -ENOMEM; in ipu_probe()
1392 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1393 if (IS_ERR(ipu->clk)) { in ipu_probe()
1394 ret = PTR_ERR(ipu->clk); in ipu_probe()
1395 dev_err(&pdev->dev, "clk_get failed with %d", ret); in ipu_probe()
1401 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1403 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); in ipu_probe()
1407 ipu->dev = &pdev->dev; in ipu_probe()
1408 ipu->irq_sync = irq_sync; in ipu_probe()
1409 ipu->irq_err = irq_err; in ipu_probe()
1411 ret = device_reset(&pdev->dev); in ipu_probe()
1413 dev_err(&pdev->dev, "failed to reset: %d\n", ret); in ipu_probe()
1428 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1434 dev_err(&pdev->dev, "adding client devices failed with %d\n", in ipu_probe()
1439 dev_info(&pdev->dev, "%s probed\n", devtype->name); in ipu_probe()
1449 clk_disable_unprepare(ipu->clk); in ipu_probe()
1461 clk_disable_unprepare(ipu->clk); in ipu_remove()
1466 .name = "imx-ipuv3",
1493 MODULE_ALIAS("platform:imx-ipuv3");