| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_i2c.c | 1 /*-
2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
33 * I2C driver for Freescale i.MX hardware.
36 * This driver currently implements only master-mode operations.
38 * This driver supports multi-master i2c buses, by detecting bus arbitration
41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller
81 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
82 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
83 #define I2C_CONTROL_REG 0x08 /* I2C control register */
84 #define I2C_STATUS_REG 0x0C /* I2C status register */
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| /freebsd/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-mpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - mpc5200-i2c
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| /freebsd/sys/dev/iicbus/controller/twsi/ |
| H A D | twsi.c | 1 /*-
33 * Driver for the TWSI (aka I2C, aka IIC) bus controller found on Marvell
36 * Calls to DELAY() are needed per Application Note AN-179 "TWSI Software
86 #define debugf(sc, fmt, args...) if ((sc)->debug) \
87 device_printf((sc)->dev, "%s: " fmt, __func__, ##args)
92 { -1, 0 }
100 val = bus_read_4(sc->res[0], off); in TWSI_READ()
101 if (sc->debug > 1) in TWSI_READ()
110 if (sc->debug > 1) in TWSI_WRITE()
112 bus_write_4(sc->res[0], off, val); in TWSI_WRITE()
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| /freebsd/sys/arm/ti/ |
| H A D | ti_i2c.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Driver for the I2C module on the TI SoC.
38 * This driver currently doesn't use DMA for the transfer, although I hope to
72 * I2C device driver context, a pointer to this is stored in the device
109 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
117 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
124 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
138 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
139 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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| /freebsd/sys/dev/pcf/ |
| H A D | pcf.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 static int pcf_noack(struct pcf_softc *pcf, int timeout);
62 int counter = TIMEOUT; in pcf_wait_byte()
65 while (counter--) { in pcf_wait_byte()
71 printf("pcf: timeout!\n"); in pcf_wait_byte()
91 if (sc->pcf_started) { in pcf_stop_locked()
95 sc->pcf_started = 0; in pcf_stop_locked()
100 pcf_noack(struct pcf_softc *sc, int timeout) in pcf_noack() argument
103 int k = timeout/10; in pcf_noack()
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| /freebsd/sys/dev/qcom_qup/ |
| H A D | qcom_spi_hw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 sc->config.input_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
80 sc->config.input_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
86 sc->config.output_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
88 sc->config.output_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
93 sc->config.input_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
94 sc->config.input_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
99 sc->config.output_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
100 sc->config.output_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
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| /freebsd/sys/dev/ichiic/ |
| H A D | ig4_iic.c | 38 * Intel fourth generation mobile cpus integrated I2C device.
79 * lines are taken from I2C specifications.
147 * 0 - Try read clock registers from ACPI and fallback to p.1.
148 * 1 - Calculate values based on controller type (IC clock rate).
149 * 2 - Use values inherited from DragonflyBSD driver (old behavior).
150 * 3 - Keep clock registers intact.
157 * Low-level inline support functions
162 bus_write_4(sc->regs_res, reg, value); in reg_write()
163 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); in reg_write()
171 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); in reg_read()
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/dev/sk/ |
| H A D | if_sk.c | 3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
20 * 4. Neither the name of the author nor the names of any co-contributors
36 /*-
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
176 "D-Link DGE-530T Gigabit Ethernet"
181 "D-Link DGE-530T Gigabit Ethernet"
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| /freebsd/sys/contrib/dev/athk/ath10k/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
62 /* PCI-E QCA988X V2 (Ubiquiti branded) */
65 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
66 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
67 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
68 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
69 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
70 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
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| /freebsd/sys/dev/bxe/ |
| H A D | ecore_hsi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
145 /* Up to 16 bytes of NULL-terminated string */
164 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
170 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
172 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
173 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
175 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
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| H A D | bxe_elink.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
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| /freebsd/sys/dev/sis/ |
| H A D | if_sis.c | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
19 * 4. Neither the name of the author nor the names of any co-contributors
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
54 * Both chips offer the standard bit-bang MII interface as well as
111 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
112 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
113 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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| /freebsd/sys/contrib/dev/acpica/ |
| H A D | changes.txt | 1 ----------------------------------------
6 Fix 2 critical CVE addressing memory leaks - Seunghun Han
17 ----------------------------------------
30 ----------------------------------------
35 …that the PHAT firmware health record offset works correctly, fix various sub-table offsets, preven…
37 Fix the optional table 4-byte signature. Contributed by: Daniil Tatianin <99danilt@gmail.com>
56 ----------------------------------------
71 Add new tables for various architectures/OS, mainly RISC-V and also update many more.
73 Add an option to either make the output deterministic or non-deterministic.
80 ----------------------------------------
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| /freebsd/sys/dev/ice/ |
| H A D | ice_lib.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
267 * ice_map_bar - Map PCIe BAR memory in ice_map_bar()
278 if (bar->res != NULL) { in ice_map_bar()
283 bar->rid = PCIR_BAR(bar_num);
284 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->rid,
286 if (!bar->re
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| /freebsd/sys/dev/bnxt/bnxt_en/ |
| H A D | hsi_struct_def.h | 1 /*-
34 * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
126 /* Engine CKV - Authentication tag. */
128 /* Engine CKV - The encrypted data. */
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|