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/linux/drivers/i2c/busses/
H A Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
39 #define IBMR_SDAS (1 << 0)
42 #define ICR_START (1 << 0) /* start bit */
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H A Di2c-jz4780.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 I2C bus driver
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
15 #include <linux/i2c.h>
27 #define JZ4780_I2C_CTRL 0x00
28 #define JZ4780_I2C_TAR 0x04
29 #define JZ4780_I2C_SAR 0x08
30 #define JZ4780_I2C_DC 0x10
31 #define JZ4780_I2C_SHCNT 0x14
32 #define JZ4780_I2C_SLCNT 0x18
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H A Di2c-mt65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
32 #define I2C_TRANSAC_COMP (1 << 0)
33 #define I2C_TRANSAC_START (1 << 0)
36 #define I2C_DCM_DISABLE 0x0000
37 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
38 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
39 #define I2C_SOFT_RST 0x0001
40 #define I2C_HANDSHAKE_RST 0x0020
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H A Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
35 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
50 REG_VALUES_100KHZ = 0,
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
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H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Conexant Digicolor SoCs
13 #include <linux/i2c.h>
23 #define II_CONTROL 0x0
24 #define II_CONTROL_LOCAL_RESET BIT(0)
26 #define II_CLOCKTIME 0x1
28 #define II_COMMAND 0x2
37 #define II_CMD_STATUS_NORMAL 0
42 #define II_DATA 0x3
43 #define II_INTFLAG_CLEAR 0x8
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H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/i2c.h>
25 /* I2C register address definitions */
26 #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
27 #define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
29 #define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
30 #define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
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H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
33 #define MPC_I2C_CLOCK_LEGACY 0
34 #define MPC_I2C_CLOCK_PRESERVE (~0U)
36 #define MPC_I2C_FDR 0x04
37 #define MPC_I2C_CR 0x08
38 #define MPC_I2C_SR 0x0c
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H A Di2c-octeon-core.c2 * (C) Copyright 2009-2010
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
22 #include "i2c-octeon-core.h"
25 #define TWSI_MASTER_CLK_REG_DEF_VAL 0x18
26 #define TWSI_MASTER_CLK_REG_OTX2_VAL 0x3
31 struct octeon_i2c *i2c = dev_id; in octeon_i2c_isr() local
33 i2c->int_disable(i2c); in octeon_i2c_isr()
34 wake_up(&i2c->queue); in octeon_i2c_isr()
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H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
38 #define S3C2410_IICCON 0x00
39 #define S3C2410_IICSTAT 0x04
40 #define S3C2410_IICADD 0x08
41 #define S3C2410_IICDS 0x0C
42 #define S3C2440_IICLC 0x10
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H A Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
4 * which has I2C controller in one of its downstream functions
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
22 #define SMBUS_MAST_CORE_ADDR_BASE 0x00000
23 #define SMBUS_MAST_SYS_REG_ADDR_BASE 0x01000
26 #define SMB_CORE_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x00)
30 #define SMB_CORE_CTRL_ACK BIT(0)
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H A Di2c-thunderx-pcidrv.c2 * Cavium ThunderX i2c driver.
16 #include <linux/i2c.h>
17 #include <linux/i2c-smbus.h>
24 #include "i2c-octeon-core.h"
26 #define DRV_NAME "i2c-thunderx"
28 #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012
33 #define TWSI_INT_ENA_W1C 0x1028
34 #define TWSI_INT_ENA_W1S 0x1030
38 * The interrupt will be asserted when there is non-STAT_IDLE state in the
41 static void thunder_i2c_int_enable(struct octeon_i2c *i2c) in thunder_i2c_int_enable() argument
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H A Di2c-viai2c-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "i2c-viai2c-common.h"
5 int viai2c_wait_bus_not_busy(struct viai2c *i2c) in viai2c_wait_bus_not_busy() argument
10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { in viai2c_wait_bus_not_busy()
12 dev_warn(i2c->dev, "timeout waiting for bus ready\n"); in viai2c_wait_bus_not_busy()
13 return -EBUSY; in viai2c_wait_bus_not_busy()
18 return 0; in viai2c_wait_bus_not_busy()
22 static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) in viai2c_write() argument
24 u16 val, tcr_val = i2c->tcr; in viai2c_write()
26 i2c->last = last; in viai2c_write()
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H A Di2c-viai2c-zhaoxin.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include "i2c-viai2c-common.h"
24 #define ZXI2C_REG_CLK 0x10
25 #define ZXI2C_CLK_50M BIT(0)
26 #define ZXI2C_REG_REV 0x11
27 #define ZXI2C_REG_HCR 0x12
28 #define ZXI2C_HCR_RST_FIFO GENMASK(1, 0)
29 #define ZXI2C_REG_HTDR 0x13
30 #define ZXI2C_REG_HRDR 0x14
31 #define ZXI2C_REG_HTLR 0x15
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H A Di2c-cgbc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Congatec Board Controller I2C busses driver
9 #include <linux/i2c.h>
15 #define CGBC_I2C_PRIMARY_BUS_ID 0
18 #define CGBC_I2C_CMD_START 0x40
19 #define CGBC_I2C_CMD_STAT 0x48
20 #define CGBC_I2C_CMD_DATA 0x50
21 #define CGBC_I2C_CMD_SPEED 0x58
23 #define CGBC_I2C_STAT_IDL 0x00
24 #define CGBC_I2C_STAT_DAT 0x01
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/linux/Documentation/i2c/
H A Di2c-sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Linux I2C Sysfs
10 I2C topology can be complex because of the existence of I2C MUX
11 (I2C Multiplexer). The Linux
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
14 to logical I2C bus number. This doc is aimed to fill in this gap, so the
16 the concept of logical I2C buses in the kernel, by knowing the physical I2C
17 topology and navigating through the I2C sysfs in Linux shell. This knowledge is
18 useful and essential to use ``i2c-tools`` for the purpose of development and
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/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Internal I2C bus driver for NetUP Universal Dual DVB-CI
18 #define NETUP_I2C_BUS0_ADDR 0x4800
19 #define NETUP_I2C_BUS1_ADDR 0x4840
23 #define TWI_IRQEN_COMPL 0x1
24 #define TWI_IRQEN_ANACK 0x2
25 #define TWI_IRQEN_DNACK 0x4
29 #define TWI_IRQ_TX 0x800
30 #define TWI_IRQ_RX 0x1000
33 #define TWI_TRANSFER 0x100
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-cmm.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,cmm-bmc", "aspeed,ast2500";
22 * PCA9548 (1-0077) provides 8 channels for connecting to
35 * PCA9548 (2-0071) provides 8 channels for connecting to
48 * PCA9548 (8-0077) provides 8 channels and the first 4
61 * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting
82 * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting
103 * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting
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H A Daspeed-bmc-facebook-minipack.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,minipack-bmc", "aspeed,ast2500";
23 * i2c switch 2-0070, pca9548, 8 child channels assigned
24 * with bus number 16-23.
36 * i2c switch 8-0070, pca9548, 8 child channels assigned
37 * with bus number 24-31.
49 * i2c switch 9-0070, pca9548, 8 child channels assigned
50 * with bus number 32-39.
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H A Daspeed-bmc-facebook-fuji.dts1 // SPDX-License-Identifier: GPL-2.0+
4 /dts-v1/;
6 #include <dt-bindings/leds/common.h>
7 #include "ast2600-facebook-netbmc-common.dtsi"
11 compatible = "facebook,fuji-bmc", "aspeed,ast2600";
15 * PCA9548 (2-0070) provides 8 channels connecting to
28 * PCA9548 (8-0070) provides 8 channels connecting to
41 * PCA9548 (11-0077) provides 8 channels connecting to
54 * PCA9548 (24-0071) provides 8 channels connecting to
55 * PDB-Left.
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/linux/drivers/media/pci/ddbridge/
H A Dddbridge-i2c.c1 // SPDX-License-Identifier: GPL-2.0
3 * ddbridge-i2c.c: Digital Devices bridge i2c driver
5 * Copyright (C) 2010-2017 Digital Devices GmbH
20 #include <linux/i2c.h>
25 #include "ddbridge-i2c.h"
26 #include "ddbridge-regs.h"
27 #include "ddbridge-io.h"
31 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) in ddb_i2c_cmd() argument
33 struct ddb *dev = i2c->dev; in ddb_i2c_cmd()
37 ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); in ddb_i2c_cmd()
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/linux/sound/soc/codecs/
H A Dwm2000.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm2000.c -- WM2000 ALSA Soc Audio driver
5 * Copyright 2008-2011 Wolfson Microelectronics PLC.
13 * system-specific calibration information. If supplied as a
14 * sequence of ASCII-encoded hexidecimal bytes this can be converted
17 * perl -e 'while (<>) { s/[\r\n]+// ; printf("%c", hex($_)); }'
29 #include <linux/i2c.h>
54 ANC_ACTIVE = 0,
61 struct i2c_client *i2c; member
81 static int wm2000_write(struct i2c_client *i2c, unsigned int reg, in wm2000_write() argument
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/linux/drivers/mfd/
H A D88pm860x-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C driver for Marvell 88PM860x
11 #include <linux/i2c.h>
15 int pm860x_reg_read(struct i2c_client *i2c, int reg) in pm860x_reg_read() argument
17 struct pm860x_chip *chip = i2c_get_clientdata(i2c); in pm860x_reg_read()
18 struct regmap *map = (i2c == chip->client) ? chip->regmap in pm860x_reg_read()
19 : chip->regmap_companion; in pm860x_reg_read()
24 if (ret < 0) in pm860x_reg_read()
31 int pm860x_reg_write(struct i2c_client *i2c, int reg, in pm860x_reg_write() argument
34 struct pm860x_chip *chip = i2c_get_clientdata(i2c); in pm860x_reg_write()
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/linux/Documentation/devicetree/bindings/i2c/
H A Dsamsung,s3c2410-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC I2C Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,s3c2410-i2c
17 - samsung,s3c2440-i2c
18 # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
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H A Di2c-demux-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Demultiplexer
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
13 This binding describes an I2C bus demultiplexer that uses pin multiplexing to
14 route the I2C signals, and represents the pin multiplexing configuration
15 using the pinctrl device tree bindings. This may be used to select one I2C
17 another I2C IP core on the SoC. The most simple example is to fall back to
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H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
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