1 // SPDX-License-Identifier: GPL-2.0
3  * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
4  * which has I2C controller in one of its downstream functions
6  * Copyright (C) 2021 - 2022 Microchip Technology Inc.
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
22 #define SMBUS_MAST_CORE_ADDR_BASE		0x00000
23 #define SMBUS_MAST_SYS_REG_ADDR_BASE		0x01000
26 #define SMB_CORE_CTRL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x00)
30 #define SMB_CORE_CTRL_ACK		BIT(0)
32 #define SMB_CORE_CMD_REG_OFF3	(SMBUS_MAST_CORE_ADDR_BASE + 0x0F)
33 #define SMB_CORE_CMD_REG_OFF2	(SMBUS_MAST_CORE_ADDR_BASE + 0x0E)
34 #define SMB_CORE_CMD_REG_OFF1	(SMBUS_MAST_CORE_ADDR_BASE + 0x0D)
38 #define SMB_CORE_CMD_START		BIT(0)
40 #define SMB_CORE_CMD_REG_OFF0	(SMBUS_MAST_CORE_ADDR_BASE + 0x0C)
43 #define SMB_CORE_CMD_M_RUN		BIT(0)
45 #define SMB_CORE_SR_HOLD_TIME_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x18)
55 #define SMB_CORE_COMPLETION_REG_OFF3	(SMBUS_MAST_CORE_ADDR_BASE + 0x23)
59 #define COMPLETION_MNAKX		BIT(0)
61 #define SMB_CORE_IDLE_SCALING_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x24)
87 #define SMB_CORE_CONFIG_REG3		(SMBUS_MAST_CORE_ADDR_BASE + 0x2B)
92 #define SMB_CORE_CONFIG_REG2		(SMBUS_MAST_CORE_ADDR_BASE + 0x2A)
93 #define SMB_CORE_CONFIG_REG1		(SMBUS_MAST_CORE_ADDR_BASE + 0x29)
98 #define SMB_CONFIG1_FEN			BIT(0)
100 #define SMB_CORE_BUS_CLK_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x2C)
103  * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock
104  * periods that make up the low phase of the I2C/SMBus bus clock at X KHz.
111  * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock
112  * periods that make up the high phase of the I2C/SMBus bus clock at X KHz.
125 #define SMB_CORE_CLK_SYNC_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x3C)
136 #define SMB_CORE_DATA_TIMING_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x40)
186 #define SMB_CORE_TO_SCALING_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x44)
190  * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x
198  * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
199  * SMBus Controller Cumulative Time-Out duration =
200  * CTRL_CUM_TIME_OUT_XK_TICKS[7:0] x Baud_Clock_Period x 2048
207  * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration.
208  * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x
217  * Clock High time out period = CLOCK_HIGH_TIME_OUT_XK[7:0] x Baud_Clock_Period x 8
233 #define I2C_SCL_PAD_CTRL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x100)
234 #define I2C_SDA_PAD_CTRL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x101)
240 #define I2C_OUTPUT_EN			BIT(0)
242 #define SMBUS_CONTROL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x200)
247 #define CTL_RUN				BIT(0)
249 #define I2C_DIRN_WRITE			0
252 #define SMBUS_STATUS_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x204)
258 #define STA_BUF_EMPTY			BIT(0)
260 #define SMBUS_INTR_STAT_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x208)
265 #define INTR_STAT_BUF_EMPTY		BIT(0)
267 #define SMBUS_INTR_MSK_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x20C)
272 #define INTR_MSK_BUF_EMPTY		BIT(0)
278 #define SMBUS_MCU_COUNTER_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x214)
280 #define SMBALERT_MST_PAD_CTRL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x230)
282 #define SMBALERT_MST_PU			BIT(0)
284 #define SMBUS_GEN_INT_STAT_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x23C)
286 #define SMBUS_GEN_INT_MASK_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x240)
293 #define I2C_WAKE_INTR_MASK		BIT(0)
300 #define SMBUS_RESET_REG		(SMBUS_MAST_CORE_ADDR_BASE + 0x248)
304 #define SMBUS_MST_BUF		(SMBUS_MAST_CORE_ADDR_BASE + 0x280)
306 #define SMBUS_BUF_MAX_SIZE		0x80
316 #define SMB_GPR_REG		(SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0c00 + \
317 				0x00)
320 #define SMB_GPR_LOCK_REG	(SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0000 + \
321 				0x00A0)
334 static int set_sys_lock(struct pci1xxxx_i2c *i2c)  in set_sys_lock()  argument
336 	void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;  in set_sys_lock()
342 		return -EPERM;  in set_sys_lock()
344 	return 0;  in set_sys_lock()
347 static int release_sys_lock(struct pci1xxxx_i2c *i2c)  in release_sys_lock()  argument
349 	void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;  in release_sys_lock()
354 		return 0;  in release_sys_lock()
356 	writel(0, p);  in release_sys_lock()
359 		return -EPERM;  in release_sys_lock()
361 	return 0;  in release_sys_lock()
364 static void pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk)  in pci1xxxx_ack_high_level_intr()  argument
366 	writew(intr_msk, i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF);  in pci1xxxx_ack_high_level_intr()
369 static void pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c *i2c,  in pci1xxxx_i2c_configure_smbalert_pin()  argument
372 	void __iomem *p = i2c->i2c_base + SMBALERT_MST_PAD_CTRL_REG_OFF;  in pci1xxxx_i2c_configure_smbalert_pin()
385 static void pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c *i2c, bool start)  in pci1xxxx_i2c_send_start_stop()  argument
387 	void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;  in pci1xxxx_i2c_send_start_stop()
405 static void pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c *i2c, bool set)  in pci1xxxx_i2c_set_clear_FW_ACK()  argument
414 	writeb(regval, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);  in pci1xxxx_i2c_set_clear_FW_ACK()
417 static void pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,  in pci1xxxx_i2c_buffer_write()  argument
420 	void __iomem *p = i2c->i2c_base + SMBUS_MST_BUF;  in pci1xxxx_i2c_buffer_write()
434 static void pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_enable_ESO()  argument
436 	writeb(SMB_CORE_CTRL_ESO, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);  in pci1xxxx_i2c_enable_ESO()
439 static void pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_reset_counters()  argument
441 	void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;  in pci1xxxx_i2c_reset_counters()
449 static void pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c *i2c, u8 direction)  in pci1xxxx_i2c_set_transfer_dir()  argument
451 	void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;  in pci1xxxx_i2c_set_transfer_dir()
463 static void pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c *i2c, u8 count)  in pci1xxxx_i2c_set_mcu_count()  argument
465 	writeb(count, i2c->i2c_base + SMBUS_MCU_COUNTER_REG_OFF);  in pci1xxxx_i2c_set_mcu_count()
468 static void pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c *i2c, u8 readcount)  in pci1xxxx_i2c_set_read_count()  argument
470 	writeb(readcount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF3);  in pci1xxxx_i2c_set_read_count()
473 static void pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c *i2c, u8 writecount)  in pci1xxxx_i2c_set_write_count()  argument
475 	writeb(writecount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF2);  in pci1xxxx_i2c_set_write_count()
478 static void pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_set_DMA_run()  argument
480 	void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;  in pci1xxxx_i2c_set_DMA_run()
488 static void pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_set_mrun_proceed()  argument
490 	void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF0;  in pci1xxxx_i2c_set_mrun_proceed()
499 static void pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_start_DMA()  argument
501 	pci1xxxx_i2c_set_DMA_run(i2c);  in pci1xxxx_i2c_start_DMA()
502 	pci1xxxx_i2c_set_mrun_proceed(i2c);  in pci1xxxx_i2c_start_DMA()
505 static void pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c *i2c, bool enable)  in pci1xxxx_i2c_config_asr()  argument
507 	void __iomem *p = i2c->i2c_base + SMB_CORE_CONFIG_REG1;  in pci1xxxx_i2c_config_asr()
520 	struct pci1xxxx_i2c *i2c = dev;  in pci1xxxx_i2c_isr()  local
521 	void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;  in pci1xxxx_i2c_isr()
522 	void __iomem *p2 = i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF;  in pci1xxxx_i2c_isr()
536 			complete(&i2c->i2c_xfer_done);  in pci1xxxx_i2c_isr()
540 		pci1xxxx_ack_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK);  in pci1xxxx_i2c_isr()
545 		pci1xxxx_ack_high_level_intr(i2c, SMBALERT_INTR_MASK);  in pci1xxxx_i2c_isr()
551 static void pci1xxxx_i2c_set_count(struct pci1xxxx_i2c *i2c, u8 mcucount,  in pci1xxxx_i2c_set_count()  argument
554 	pci1xxxx_i2c_set_mcu_count(i2c, mcucount);  in pci1xxxx_i2c_set_count()
555 	pci1xxxx_i2c_set_write_count(i2c, writecount);  in pci1xxxx_i2c_set_count()
556 	pci1xxxx_i2c_set_read_count(i2c, readcount);  in pci1xxxx_i2c_set_count()
559 static void pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c *i2c, bool enable)  in pci1xxxx_i2c_set_readm()  argument
561 	void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;  in pci1xxxx_i2c_set_readm()
573 static void pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 ack_intr_msk)  in pci1xxxx_ack_nw_layer_intr()  argument
575 	writeb(ack_intr_msk, i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF);  in pci1xxxx_ack_nw_layer_intr()
578 static void pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c *i2c,  in pci1xxxx_config_nw_layer_intr()  argument
581 	void __iomem *p = i2c->i2c_base + SMBUS_INTR_MSK_REG_OFF;  in pci1xxxx_config_nw_layer_intr()
593 static void pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c *i2c, bool enable)  in pci1xxxx_i2c_config_padctrl()  argument
595 	void __iomem *p1 = i2c->i2c_base + I2C_SCL_PAD_CTRL_REG_OFF;  in pci1xxxx_i2c_config_padctrl()
596 	void __iomem *p2 = i2c->i2c_base + I2C_SDA_PAD_CTRL_REG_OFF;  in pci1xxxx_i2c_config_padctrl()
616 static void pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_set_mode()  argument
618 	void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;  in pci1xxxx_i2c_set_mode()
622 	if (i2c->flags & I2C_FLAGS_DIRECT_MODE)  in pci1xxxx_i2c_set_mode()
630 static void pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c *i2c,  in pci1xxxx_i2c_config_high_level_intr()  argument
633 	void __iomem *p = i2c->i2c_base + SMBUS_GEN_INT_MASK_REG_OFF;  in pci1xxxx_i2c_config_high_level_intr()
644 static void pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c *i2c, bool enable)  in pci1xxxx_i2c_configure_core_reg()  argument
646 	void __iomem *p1 = i2c->i2c_base + SMB_CORE_CONFIG_REG1;  in pci1xxxx_i2c_configure_core_reg()
647 	void __iomem *p3 = i2c->i2c_base + SMB_CORE_CONFIG_REG3;  in pci1xxxx_i2c_configure_core_reg()
665 static void pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_set_freq()  argument
667 	void __iomem *bp = i2c->i2c_base;  in pci1xxxx_i2c_set_freq()
675 	switch (i2c->freq) {  in pci1xxxx_i2c_set_freq()
706 static void pci1xxxx_i2c_init(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_init()  argument
708 	void __iomem *p2 = i2c->i2c_base + SMBUS_STATUS_REG_OFF;  in pci1xxxx_i2c_init()
709 	void __iomem *p1 = i2c->i2c_base + SMB_GPR_REG;  in pci1xxxx_i2c_init()
713 	ret = set_sys_lock(i2c);  in pci1xxxx_i2c_init()
714 	if (ret == -EPERM) {  in pci1xxxx_i2c_init()
716 		 * Configure I2C Fast Mode as default frequency if unable  in pci1xxxx_i2c_init()
719 		regval = 0;  in pci1xxxx_i2c_init()
722 		release_sys_lock(i2c);  in pci1xxxx_i2c_init()
726 	case 0:  in pci1xxxx_i2c_init()
727 		i2c->freq = I2C_MAX_FAST_MODE_FREQ;  in pci1xxxx_i2c_init()
728 		pci1xxxx_i2c_set_freq(i2c);  in pci1xxxx_i2c_init()
731 		i2c->freq = I2C_MAX_STANDARD_MODE_FREQ;  in pci1xxxx_i2c_init()
732 		pci1xxxx_i2c_set_freq(i2c);  in pci1xxxx_i2c_init()
735 		i2c->freq = I2C_MAX_FAST_MODE_PLUS_FREQ;  in pci1xxxx_i2c_init()
736 		pci1xxxx_i2c_set_freq(i2c);  in pci1xxxx_i2c_init()
743 	pci1xxxx_i2c_config_padctrl(i2c, true);  in pci1xxxx_i2c_init()
744 	i2c->flags |= I2C_FLAGS_DIRECT_MODE;  in pci1xxxx_i2c_init()
745 	pci1xxxx_i2c_set_mode(i2c);  in pci1xxxx_i2c_init()
753 	/* Configure core I2c control registers. */  in pci1xxxx_i2c_init()
754 	pci1xxxx_i2c_configure_core_reg(i2c, true);  in pci1xxxx_i2c_init()
757 	 * Enable pull-up for the SMB alert pin which is just used for  in pci1xxxx_i2c_init()
760 	pci1xxxx_i2c_configure_smbalert_pin(i2c, true);  in pci1xxxx_i2c_init()
763 static void pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c *i2c)  in pci1xxxx_i2c_clear_flags()  argument
768 	pci1xxxx_i2c_reset_counters(i2c);  in pci1xxxx_i2c_clear_flags()
772 	writeb(regval, i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3);  in pci1xxxx_i2c_clear_flags()
773 	reinit_completion(&i2c->i2c_xfer_done);  in pci1xxxx_i2c_clear_flags()
774 	pci1xxxx_ack_nw_layer_intr(i2c, ALL_NW_LAYER_INTERRUPTS);  in pci1xxxx_i2c_clear_flags()
775 	pci1xxxx_ack_high_level_intr(i2c, ALL_HIGH_LAYER_INTR);  in pci1xxxx_i2c_clear_flags()
778 static int pci1xxxx_i2c_read(struct pci1xxxx_i2c *i2c, u8 slaveaddr,  in pci1xxxx_i2c_read()  argument
781 	void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;  in pci1xxxx_i2c_read()
782 	void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;  in pci1xxxx_i2c_read()
783 	void __iomem *p3 = i2c->i2c_base + SMBUS_MST_BUF;  in pci1xxxx_i2c_read()
787 	int retval = 0;  in pci1xxxx_i2c_read()
792 	/* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */  in pci1xxxx_i2c_read()
793 	pci1xxxx_i2c_enable_ESO(i2c);  in pci1xxxx_i2c_read()
794 	pci1xxxx_i2c_clear_flags(i2c);  in pci1xxxx_i2c_read()
795 	pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);  in pci1xxxx_i2c_read()
796 	pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);  in pci1xxxx_i2c_read()
799 	 * The I2C transfer could be more than 128 bytes. Our Core is  in pci1xxxx_i2c_read()
801 	 * As far as the I2C read is concerned, initailly send the  in pci1xxxx_i2c_read()
807 	for (count = 0; count < total_len; count += transferlen) {  in pci1xxxx_i2c_read()
813 		writeb(0, p1);  in pci1xxxx_i2c_read()
814 		remainingbytes = total_len - count;  in pci1xxxx_i2c_read()
819 		 * For I2C read transaction of more than BUF_SIZE, NACK should  in pci1xxxx_i2c_read()
827 		    (i2c->flags & I2C_FLAGS_STOP)) {  in pci1xxxx_i2c_read()
828 			pci1xxxx_i2c_set_clear_FW_ACK(i2c, false);  in pci1xxxx_i2c_read()
829 			pci1xxxx_i2c_send_start_stop(i2c, 0);  in pci1xxxx_i2c_read()
831 			pci1xxxx_i2c_set_clear_FW_ACK(i2c, true);  in pci1xxxx_i2c_read()
835 		if (count == 0) {  in pci1xxxx_i2c_read()
836 			pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);  in pci1xxxx_i2c_read()
837 			pci1xxxx_i2c_send_start_stop(i2c, 1);  in pci1xxxx_i2c_read()
839 			/* Write I2c buffer with just the slave addr. */  in pci1xxxx_i2c_read()
840 			pci1xxxx_i2c_buffer_write(i2c, slaveaddr, 0, NULL);  in pci1xxxx_i2c_read()
843 			pci1xxxx_i2c_set_count(i2c, 1, 1, transferlen);  in pci1xxxx_i2c_read()
849 			pci1xxxx_i2c_config_asr(i2c, true);  in pci1xxxx_i2c_read()
850 			if (i2c->flags & I2C_FLAGS_SMB_BLK_READ)  in pci1xxxx_i2c_read()
851 				pci1xxxx_i2c_set_readm(i2c, true);  in pci1xxxx_i2c_read()
853 			pci1xxxx_i2c_set_count(i2c, 0, 0, transferlen);  in pci1xxxx_i2c_read()
854 			pci1xxxx_i2c_config_asr(i2c, false);  in pci1xxxx_i2c_read()
855 			pci1xxxx_i2c_clear_flags(i2c);  in pci1xxxx_i2c_read()
856 			pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_READ);  in pci1xxxx_i2c_read()
860 		pci1xxxx_i2c_start_DMA(i2c);  in pci1xxxx_i2c_read()
863 		time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,  in pci1xxxx_i2c_read()
865 		if (time_left == 0) {  in pci1xxxx_i2c_read()
866 			/* Reset the I2C core to release the bus lock. */  in pci1xxxx_i2c_read()
867 			pci1xxxx_i2c_init(i2c);  in pci1xxxx_i2c_read()
868 			retval = -ETIMEDOUT;  in pci1xxxx_i2c_read()
878 			retval = -ETIMEDOUT;  in pci1xxxx_i2c_read()
882 		if (i2c->flags & I2C_FLAGS_SMB_BLK_READ) {  in pci1xxxx_i2c_read()
883 			buf[0] = readb(p3);  in pci1xxxx_i2c_read()
884 			read_count = buf[0];  in pci1xxxx_i2c_read()
893 	pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);  in pci1xxxx_i2c_read()
894 	pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);  in pci1xxxx_i2c_read()
895 	pci1xxxx_i2c_config_asr(i2c, false);  in pci1xxxx_i2c_read()
899 static int pci1xxxx_i2c_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,  in pci1xxxx_i2c_write()  argument
902 	void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;  in pci1xxxx_i2c_write()
903 	void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;  in pci1xxxx_i2c_write()
908 	int retval = 0;  in pci1xxxx_i2c_write()
912 	/* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */  in pci1xxxx_i2c_write()
913 	pci1xxxx_i2c_enable_ESO(i2c);  in pci1xxxx_i2c_write()
916 	pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);  in pci1xxxx_i2c_write()
917 	pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);  in pci1xxxx_i2c_write()
918 	pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);  in pci1xxxx_i2c_write()
921 	 * The i2c transfer could be more than 128 bytes. Our Core is  in pci1xxxx_i2c_write()
924 	for (count = 0; count < total_len; count += transferlen) {  in pci1xxxx_i2c_write()
929 		writeb(0, p1);  in pci1xxxx_i2c_write()
930 		pci1xxxx_i2c_clear_flags(i2c);  in pci1xxxx_i2c_write()
931 		remainingbytes = total_len - count;  in pci1xxxx_i2c_write()
934 		if (count == 0) {  in pci1xxxx_i2c_write()
935 			pci1xxxx_i2c_send_start_stop(i2c, 1);  in pci1xxxx_i2c_write()
937 			/* -1 for the slave address. */  in pci1xxxx_i2c_write()
938 			transferlen = min_t(u16, SMBUS_BUF_MAX_SIZE - 1,  in pci1xxxx_i2c_write()
940 			pci1xxxx_i2c_buffer_write(i2c, slaveaddr,  in pci1xxxx_i2c_write()
943 			 * The actual number of bytes written on the I2C bus  in pci1xxxx_i2c_write()
949 			pci1xxxx_i2c_buffer_write(i2c, 0, transferlen, &buf[count]);  in pci1xxxx_i2c_write()
953 		pci1xxxx_i2c_set_count(i2c, actualwritelen, actualwritelen, 0);  in pci1xxxx_i2c_write()
960 		   (i2c->flags & I2C_FLAGS_STOP))  in pci1xxxx_i2c_write()
961 			pci1xxxx_i2c_send_start_stop(i2c, 0);  in pci1xxxx_i2c_write()
963 		pci1xxxx_i2c_start_DMA(i2c);  in pci1xxxx_i2c_write()
968 		time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,  in pci1xxxx_i2c_write()
970 		if (time_left == 0) {  in pci1xxxx_i2c_write()
971 			/* Reset the I2C core to release the bus lock. */  in pci1xxxx_i2c_write()
972 			pci1xxxx_i2c_init(i2c);  in pci1xxxx_i2c_write()
973 			retval = -ETIMEDOUT;  in pci1xxxx_i2c_write()
980 			retval = -ETIMEDOUT;  in pci1xxxx_i2c_write()
986 	pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);  in pci1xxxx_i2c_write()
987 	pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);  in pci1xxxx_i2c_write()
995 	struct pci1xxxx_i2c *i2c = i2c_get_adapdata(adap);  in pci1xxxx_i2c_xfer()  local
1000 	i2c->i2c_xfer_in_progress = true;  in pci1xxxx_i2c_xfer()
1001 	for (i = 0; i < num; i++) {  in pci1xxxx_i2c_xfer()
1008 		if ((i == num - 1) || (msgs[i].flags & I2C_M_STOP))  in pci1xxxx_i2c_xfer()
1009 			i2c->flags |= I2C_FLAGS_STOP;  in pci1xxxx_i2c_xfer()
1011 			i2c->flags &= ~I2C_FLAGS_STOP;  in pci1xxxx_i2c_xfer()
1014 			i2c->flags |= I2C_FLAGS_SMB_BLK_READ;  in pci1xxxx_i2c_xfer()
1016 			i2c->flags &= ~I2C_FLAGS_SMB_BLK_READ;  in pci1xxxx_i2c_xfer()
1019 			retval = pci1xxxx_i2c_read(i2c, slaveaddr,  in pci1xxxx_i2c_xfer()
1022 			retval = pci1xxxx_i2c_write(i2c, slaveaddr,  in pci1xxxx_i2c_xfer()
1025 		if (retval < 0)  in pci1xxxx_i2c_xfer()
1028 	i2c->i2c_xfer_in_progress = false;  in pci1xxxx_i2c_xfer()
1030 	if (retval < 0)  in pci1xxxx_i2c_xfer()
1061 	.name	= "PCI1xxxx I2C Adapter",
1068 	struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);  in pci1xxxx_i2c_suspend()  local
1069 	void __iomem *p = i2c->i2c_base + SMBUS_RESET_REG;  in pci1xxxx_i2c_suspend()
1073 	i2c_mark_adapter_suspended(&i2c->adap);  in pci1xxxx_i2c_suspend()
1076 	 * If the system is put into 'suspend' state when the I2C transfer is in  in pci1xxxx_i2c_suspend()
1079 	while (i2c->i2c_xfer_in_progress)  in pci1xxxx_i2c_suspend()
1082 	pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, true);  in pci1xxxx_i2c_suspend()
1096 	return 0;  in pci1xxxx_i2c_suspend()
1101 	struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);  in pci1xxxx_i2c_resume()  local
1102 	void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;  in pci1xxxx_i2c_resume()
1103 	void __iomem *p2 = i2c->i2c_base + SMBUS_RESET_REG;  in pci1xxxx_i2c_resume()
1109 	pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, false);  in pci1xxxx_i2c_resume()
1113 	i2c_mark_adapter_resumed(&i2c->adap);  in pci1xxxx_i2c_resume()
1115 	return 0;  in pci1xxxx_i2c_resume()
1123 	struct pci1xxxx_i2c *i2c = data;  in pci1xxxx_i2c_shutdown()  local
1125 	pci1xxxx_i2c_config_padctrl(i2c, false);  in pci1xxxx_i2c_shutdown()
1126 	pci1xxxx_i2c_configure_core_reg(i2c, false);  in pci1xxxx_i2c_shutdown()
1132 	struct device *dev = &pdev->dev;  in pci1xxxx_i2c_probe_pci()
1133 	struct pci1xxxx_i2c *i2c;  in pci1xxxx_i2c_probe_pci()  local
1136 	i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);  in pci1xxxx_i2c_probe_pci()
1137 	if (!i2c)  in pci1xxxx_i2c_probe_pci()
1138 		return -ENOMEM;  in pci1xxxx_i2c_probe_pci()
1140 	pci_set_drvdata(pdev, i2c);  in pci1xxxx_i2c_probe_pci()
1141 	i2c->i2c_xfer_in_progress = false;  in pci1xxxx_i2c_probe_pci()
1153 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));  in pci1xxxx_i2c_probe_pci()
1154 	if (ret < 0)  in pci1xxxx_i2c_probe_pci()
1157 	i2c->i2c_base =	pcim_iomap_table(pdev)[0];  in pci1xxxx_i2c_probe_pci()
1158 	init_completion(&i2c->i2c_xfer_done);  in pci1xxxx_i2c_probe_pci()
1159 	pci1xxxx_i2c_init(i2c);  in pci1xxxx_i2c_probe_pci()
1161 	ret = devm_add_action(dev, pci1xxxx_i2c_shutdown, i2c);  in pci1xxxx_i2c_probe_pci()
1166 	if (ret < 0)  in pci1xxxx_i2c_probe_pci()
1169 	ret = devm_request_irq(dev, pci_irq_vector(pdev, 0), pci1xxxx_i2c_isr,  in pci1xxxx_i2c_probe_pci()
1170 			       0, pci_name(pdev), i2c);  in pci1xxxx_i2c_probe_pci()
1174 	i2c->adap = pci1xxxx_i2c_ops;  in pci1xxxx_i2c_probe_pci()
1175 	i2c->adap.dev.parent = dev;  in pci1xxxx_i2c_probe_pci()
1177 	snprintf(i2c->adap.name, sizeof(i2c->adap.name),  in pci1xxxx_i2c_probe_pci()
1178 		 "MCHP PCI1xxxx i2c adapter at %s", pci_name(pdev));  in pci1xxxx_i2c_probe_pci()
1180 	i2c_set_adapdata(&i2c->adap, i2c);  in pci1xxxx_i2c_probe_pci()
1182 	ret = devm_i2c_add_adapter(dev, &i2c->adap);  in pci1xxxx_i2c_probe_pci()
1184 		return dev_err_probe(dev, ret, "i2c add adapter failed\n");  in pci1xxxx_i2c_probe_pci()
1186 	return 0;  in pci1xxxx_i2c_probe_pci()
1190 	{ PCI_VDEVICE(EFAR, 0xA003) },
1191 	{ PCI_VDEVICE(EFAR, 0xA013) },
1192 	{ PCI_VDEVICE(EFAR, 0xA023) },
1193 	{ PCI_VDEVICE(EFAR, 0xA033) },
1194 	{ PCI_VDEVICE(EFAR, 0xA043) },
1200 	.name		= "i2c-mchp-pci1xxxx",
1212 MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx I2C bus driver");