i\-tlb\-size (full) in projects: freebsd

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:i +full:- +full:tlb +full:- +full:size (Results 1 – 25 of 105) sorted by relevance

12 3 4 5

/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A D	fu540-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size [all...]`
H A D	fu740-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cell [all...]`
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A D	microchip-mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 6 #include "microchip-mpfs-fabric.dtsi" 9 #address-cells = <2>; 10 #size-cells = <2>; 15 #address-cells = <1>; 16 #size-cells = <0>; 21 i-cache-block-size = <64>; [all …]`
H A D	mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 21 i-cache-block-size = <64>; [all …]`
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A D	jh7100.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; 18 #size-cells = <0>; 21 compatible = "sifive,u74-mc", "riscv"; 23 d-cache-block-size = <64>; [all …]`
H A D	jh7110.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive,jh7110-crg.h> 9 #include <dt-bindings/power/starfive,jh7110-pmu.h> 10 #include <dt-bindings/reset/starfive,jh7110-crg.h> 11 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 19 #address-cells = <1>; 20 #size-cells = <0>; [all …]`
/freebsd/sys/contrib/device-tree/src/powerpc/
H A D	microwatt.dts	`1 /dts-v1/; 4 #size-cells = <0x02>; 5 #address-cells = <0x02>; 6 model-name = "microwatt"; 7 compatible = "microwatt-soc"; 13 reserved-memory { 14 #size-cells = <0x02>; 15 #address-cells = <0x02>; 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; [all …]`
/freebsd/sys/netinet/
H A D	tcp_log_buf.c	2 /- 3 SPDX-License-Identifier: BSD-2-Clause 5 * Copyright (c) 2016-2018 Netflix, Inc. 155 "Logging mode for auto-selected sessions (default is TCP_LOG_STATE_TAIL)"); 159 "Auto-select from all sessions (rather than just those with IDs)"); 268 #define TCPID_BUCKET_LOCK_INIT(tlb) mtx_init(&((tlb)->tlb_mtx), "tcp log id bucket", NULL, MTX_DEF) argument 269 #define TCPID_BUCKET_LOCK_DESTROY(tlb) mtx_destroy(&((tlb)->tlb_mtx)) argument 270 #define TCPID_BUCKET_LOCK(tlb) mtx_lock(&((tlb)->tlb_mtx)) argument 271 #define TCPID_BUCKET_UNLOCK(tlb) mtx_unlock(&((tlb)->tlb_mtx)) argument 272 #define TCPID_BUCKET_LOCK_ASSERT(tlb) mtx_assert(&((tlb)->tlb_mtx), MA_OWNED) argument [all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A D	cpus.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V CPUs 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 This document uses some terminology common to the RISC-V community 19 mandated by the RISC-V ISA: a PC and some registers. This 27 - $ref: /schemas/cpu.yaml# [all …]`
/freebsd/sys/x86/x86/
H A D	identcpu.c	1 /- 71 #include <xen/xen-os.h> 124 u_int cpu_mon_min_size; / MONITOR minimum range size, bytes / 125 u_int cpu_mon_max_size; / MONITOR minimum range size, bytes */ 154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine() 252 u_int regs[4], i; in printcpuinfo() 266 for (i = 0x80000002; i < 0x80000005; i++) { in printcpuinfo() 267 do_cpuid(i, reg in printcpuinfo() 249 u_int regs[4], i; printcpuinfo() local 1382 int i; identify_hypervisor_cpuid_base() local 1792 int i; find_cpu_vendor_id() local 1801 print_AMD_assoc(int i) print_AMD_assoc() argument 1810 print_AMD_l2_assoc(int i) print_AMD_l2_assoc() argument [all...]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K" 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… [all …]
H A D	other.json	50 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 65 "BriefDescription": "Read-write data cache collisions" 75 … "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)" 85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac… 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 200 "BriefDescription": "Read-write data cache collisions" 280 …-word boundary, which causes it to require an additional slice than than what normally would be re… 300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" 395 …-word boundary, which causes it to require an additional slice than than what normally would be re… 430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)" [all …]
/freebsd/sys/arm/include/
H A D	cpu.h	1 /- 45 unconditionally with -DSMP. Although it looks like a bug, 140 /* TLB / 142 _WF0(_CP15_TLBIALL, CP15_TLBIALL) / Invalidate entire unified TLB / in _WF0() 144 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) / Invalidate entire unified TLB IS / in _WF0() 146 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) / Invalidate unified TLB by ASID / in _WF0() 148 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) / Invalidate unified TLB by ASID IS / in _WF0() 150 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) / Invalidate unified TLB by MVA, all ASID / in _WF0() 152 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) / Invalidate unified TLB by MVA, all ASID IS / in _WF0() 154 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) / Invalidate unified TLB by MVA */ in _WF0() [all …]
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A D	TreeTransform.h	1 //===------- TreeTransform.h - Semantic Tree Transformation ------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 66 /// transformation is performed for non-type template parameters and 69 /// This tree-transformation template uses static polymorphism to allow 86 /// most coarse-grained transformations involve replacing TransformType(), 91 /// For more fine-grained transformations, subclasses can replace any of the 106 /// default locations and entity names used for type-checking 110 /// Private RAII object that helps us forget and then re-remember [all …]
H A D	SemaCXXScopeSpec.cpp	1 //===--- SemaCXXScopeSpec.cpp - Semantic Analysis for C++ scope specifiers-===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 32 const Type Ty = T->getCanonicalTypeInternal().getTypePtr(); in getCurrentInstantiationOf() 34 CXXRecordDecl Record = cast<CXXRecordDecl>(RecordTy->getDecl()); in getCurrentInstantiationOf() 35 if (!Record->isDependentContext() \|\| in getCurrentInstantiationOf() 36 Record->isCurrentInstantiation(CurContext)) in getCurrentInstantiationOf() 41 return cast<InjectedClassNameType>(Ty)->getDecl(); in getCurrentInstantiationOf() 47 if (!T->isDependentType()) in computeDeclContext() [all …]
H A D	SemaTemplateInstantiate.cpp	1 //===------- SemaTemplateInstantiate.cpp - C++ Template Instantiation ------===/ 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 //===----------------------------------------------------------------------===/ 10 //===----------------------------------------------------------------------===/ 49 //===----------------------------------------------------------------------===/ 51 //===----------------------------------------------------------------------===/ 76 return ChangeDecl(CurDecl->getDeclContext()); in UseNextDecl() 95 LambdaCallOperator->getDescribedTemplate()); in getPrimaryTemplateOfGenericLambda() 96 FTD && FTD->getInstantiatedFromMemberTemplate()) { in getPrimaryTemplateOfGenericLambda() 98 FTD->getInstantiatedFromMemberTemplate()->getTemplatedDecl(); in getPrimaryTemplateOfGenericLambda() [all …]
/freebsd/sys/powerpc/booke/
H A D	trap_subr.S	`1 /- 2 Copyright (C) 2006-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 29 /- 72 SPRG0 - pcpu pointer 73 * SPRG1 - all interrupts except TLB miss, critical, machine check 74 * SPRG2 - critical 75 * SPRG3 - machine check 76 * SPRG4-6 - scratch 80 /* Get the per-CPU data structure / 94 sprg_sp - SPRG{1-3} reg used to temporarily store the SP [all …]`
H A D	pmap.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 39 * 32-bit pmap: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 210 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.", 216 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.", 222 "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.", [all …]
/freebsd/sys/i386/i386/
H A D	mp_machdep.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 154 unsigned int i; in alloc_ap_trampoline() local 158 for (i = physmap_idx; i <= physmap_idx; i -= 2) { in alloc_ap_trampoline() 164 if (physmap[i] >= MiB(1) \|\| in alloc_ap_trampoline() 165 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) < in alloc_ap_trampoline() 174 if (physmap[i + 1] < MiB(1)) { in alloc_ap_trampoline() 175 boot_address = trunc_page(physmap[i + 1]); in alloc_ap_trampoline() 176 if ((physmap[i + 1] - boot_address) < bootMP_size) in alloc_ap_trampoline() 177 boot_address -= round_page(bootMP_size); in alloc_ap_trampoline() [all …]
/freebsd/lib/libpmc/
H A D	pmc.haswell.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 325462-045US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 122 Any other request that crosses IDI, including I/O. 128 M-state initial lookup stat in L3. [all …]`
H A D	pmc.haswellxeon.3	`46 .Bl -tag -width "Li PMC_CLASS_IAP" 48 Fixed-function counters that count only one hardware event per counter. 60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62 .%N "Order Number: 325462-052US" 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 90 Configure the Off-core Response bits. 91 .Bl -tag -width indent 123 Any other request that crosses IDI, including I/O. 129 M-state initial lookup stat in L3. [all …]`
/freebsd/sys/amd64/amd64/
H A D	pmap.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 47 /- 49 Copyright (c) 2014-2020 The FreeBSD Foundation 55 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 92 * this module may throw away valid virtual-to-physical 94 * of virtual-to-physical mappings must be done as 98 * make virtual-to-physical map invalidates expensive, 181 return ((pmap->pm_type == PT_EPT) \|\| (pmap->pm_type == PT_RVI)); in pmap_type_guest() [all …]
/freebsd/sys/dev/agp/
H A D	agp_ali.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 50 u_int32_t initial_aperture; /* aperture size at startup / 104 sc->initial_aperture = AGP_GET_APERTURE(dev); in agp_ali_attach() 105 if (sc->initial_aperture == 0) { in agp_ali_attach() 106 device_printf(dev, "bad initial aperture size, disabling\n"); in agp_ali_attach() 117 aperture so that the gatt size reduces. in agp_ali_attach() 124 sc->gatt = gatt; in agp_ali_attach() 128 pci_write_config(dev, AGP_ALI_ATTBASE, gatt->ag_physical \| in agp_ali_attach() 131 /* Enable the TLB. */ in agp_ali_attach() [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 149 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.", 155 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.", 167 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB.", 173 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.", 179 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.", [all …]

12 3 4 5