Lines Matching +full:i +full:- +full:tlb +full:- +full:size

46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
62 .%N "Order Number: 325462-052US"
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
91 .Bl -tag -width indent
123 Any other request that crosses IDI, including I/O.
129 M-state initial lookup stat in L3.
131 E-state.
133 S-state.
135 F-state.
139 No details on snoop-related information.
149 Hit denotes a cache-line was valid before snoop effect.
160 A snoop was needed and it HitM-ed in local or remote cache.
161 HitM denotes a cache-line was in modified state before effect as a results of snoop.
167 Target was non-DRAM system address.
175 Configure the PMC to count the number of de-asserted to asserted
202 .Bl -tag -width indent
209 Speculative cache-line split load uops dispatched to
213 Speculative cache-line split Store-address uops
221 Misses in all TLB levels that cause a page walk of any
222 page size.
226 that caused 4K page walks in any TLB levels.
230 that caused 2M/4M page walks in any TLB levels.
233 Completed page walks in any TLB of any page size
250 DTLB demand load misses with low part of linear-to-
265 Number of flags-merge uops allocated.
359 Miss in all TLB levels causes an page walk of any
360 page size (4K/2M/4M/1G).
364 more TLB levels of 4K page structure.
368 more TLB levels of 2M/4M page structure.
371 Completed page walks due to store miss in any TLB
372 levels of any page size (4K/2M/4M/1G).
384 Store operations that miss the first TLB level but hit
388 DTLB store misses with low part of linear-to-physical
392 Non-SW-prefetch load dispatches that hit fill buffer
396 Non-SW-prefetch load dispatches that hit fill buffer
508 size.
519 Completed page walks in ITLB of any page size.
596 Count number of non-delivered uops to RAT per
643 Cycles stalled due to re-order buffer full.
678 Counts total number of uops to be executed per-core
714 DTLB flush attempts of the thread-specific entries.
727 Number of transitions from AVX-256 to legacy SSE
731 Number of transitions from SSE to AVX-256 when
739 Counts the number of micro-ops retired, Use
752 Number of self-modifying-code machine clears
858 and cross-core snoop missed in on-pkg core cache.
862 cross-core snoop hits in on-pkg core cache.
877 Number of front end re-steers due to BPU
904 .It Li L2_LINES_IN.I
906 L2 cache lines in I state filling L2.