1 /*-
45  * unconditionally with -DSMP. Although it looks like a bug,
140 /* TLB */
142 _WF0(_CP15_TLBIALL, CP15_TLBIALL)		/* Invalidate entire unified TLB */  in _WF0()
144 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)		/* Invalidate entire unified TLB IS */  in _WF0()
146 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))		/* Invalidate unified TLB by ASID */  in _WF0()
148 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))	/* Invalidate unified TLB by ASID IS */  in _WF0()
150 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))		/* Invalidate unified TLB by MVA, all ASID */  in _WF0()
152 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))	/* Invalidate unified TLB by MVA, all ASID IS */  in _WF0()
154 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))		/* Invalidate unified TLB by MVA */  in _WF0()
273 /* Generic Timer registers - only use when you know the hardware is available */  in _WF0()
310  * TLB maintenance operations.  in _WF0()
313 /* Local (i.e. not broadcasting ) operations.  */  in _WF0()
315 /* Flush all TLB entries (even global). */  in _WF0()
325 /* Flush all not global TLB entries. */
335 /* Flush single TLB entry (even global). */
347 /* Flush range of TLB entries (even global). */
349 tlb_flush_range_local(vm_offset_t va, vm_size_t size)  in tlb_flush_range_local()  argument
351 	vm_offset_t eva = va + size;  in tlb_flush_range_local()
354 	KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,  in tlb_flush_range_local()
355 	    size));  in tlb_flush_range_local()
405 tlb_flush_range(vm_offset_t va,  vm_size_t size)  in tlb_flush_range()  argument
407 	vm_offset_t eva = va + size;  in tlb_flush_range()
410 	KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,  in tlb_flush_range()
411 	    size));  in tlb_flush_range()
431 #define tlb_flush_range(va, size) 	tlb_flush_range_local(va, size)  argument
439 /*  Sync I and D caches to PoU */
441 icache_sync(vm_offset_t va, vm_size_t size)  in icache_sync()  argument
443 	vm_offset_t eva = va + size;  in icache_sync()
460 /*  Invalidate I cache */
486 /* Write back D-cache to PoU */
488 dcache_wb_pou(vm_offset_t va, vm_size_t size)  in dcache_wb_pou()  argument
490 	vm_offset_t eva = va + size;  in dcache_wb_pou()
501  * Invalidate D-cache to PoC
509 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)  in dcache_inv_poc()  argument
511 	vm_offset_t eva = va + size;  in dcache_inv_poc()
515 	cpu_l2cache_inv_range(pa, size);  in dcache_inv_poc()
526  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
536 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)  in dcache_inv_poc_dma()  argument
538 	vm_offset_t eva = va + size;  in dcache_inv_poc_dma()
549 	cpu_l2cache_inv_range(pa, size);  in dcache_inv_poc_dma()
553  * Write back D-cache to PoC
560 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)  in dcache_wb_poc()  argument
562 	vm_offset_t eva = va + size;  in dcache_wb_poc()
571 	cpu_l2cache_wb_range(pa, size);  in dcache_wb_poc()
574 /* Write back and invalidate D-cache to PoC */
576 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)  in dcache_wbinv_poc()  argument
579 	vm_offset_t eva = sva + size;  in dcache_wbinv_poc()
590 	cpu_l2cache_wbinv_range(pa, size);  in dcache_wbinv_poc()
678 		/* Make sure there was no wrap-around while we read the lo half. */  in get_cyclecount()
689 #define TRAPF_USERMODE(frame)	((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
691 #define TRAPF_PC(tfp)		((tfp)->tf_pc)
693 #define cpu_getstack(td)	((td)->td_frame->tf_usr_sp)
694 #define cpu_setstack(td, sp)	((td)->td_frame->tf_usr_sp = (sp))
704  * Params passed into initarm. If you change the size of this you will
709 	register_t	abp_size;	/* Size of this structure */