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Searched full:hwirq (Results 1 – 25 of 268) sorted by relevance

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/linux/drivers/irqchip/
H A Dirq-sp7021-intc.c81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value) in sp_intc_assign_bit() argument
87 offset = (hwirq / 32) * 4; in sp_intc_assign_bit()
93 mask |= BIT(hwirq % 32); in sp_intc_assign_bit()
95 mask &= ~BIT(hwirq % 32); in sp_intc_assign_bit()
102 u32 hwirq = d->hwirq; in sp_intc_ack_irq() local
104 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND in sp_intc_ack_irq()
105 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW)); in sp_intc_ack_irq()
106 ASSIGN_STATE(hwirq, _IS_ACTIVE, true); in sp_intc_ack_irq()
109 sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1); in sp_intc_ack_irq()
114 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0); in sp_intc_mask_irq()
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H A Dirq-mchp-eic.c51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
105 eic->wakeup_source |= BIT(d->hwirq); in mchp_eic_irq_set_wake()
107 eic->wakeup_source &= ~BIT(d->hwirq); in mchp_eic_irq_set_wake()
114 unsigned int hwirq; in mchp_eic_irq_suspend() local
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H A Dirq-mmp.c71 int hwirq; in icu_mask_ack_irq() local
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
95 int hwirq; in icu_mask_irq() local
98 hwirq = d->irq - data->virq_base; in icu_mask_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
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H A Dirq-mvebu-sei.c61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
63 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
76 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
84 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
90 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
146 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
201 unsigned long *hwirq, in mvebu_sei_ap_translate() argument
204 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
215 unsigned long hwirq; in mvebu_sei_ap_alloc() local
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H A Dirq-pruss-intc.c173 * @hwirq: the system event number
178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_map() argument
186 intc->event_channel[hwirq].ref_count++; in pruss_intc_map()
188 ch = intc->event_channel[hwirq].value; in pruss_intc_map()
191 pruss_intc_update_cmr(intc, hwirq, ch); in pruss_intc_map()
193 reg_idx = hwirq / 32; in pruss_intc_map()
194 val = BIT(hwirq % 32); in pruss_intc_map()
208 hwirq, ch, host); in pruss_intc_map()
216 * @hwirq: the system event number
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_unmap() argument
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H A Dirq-ls-extirq.c57 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type() local
61 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
63 mask = 1U << hwirq; in ls_extirq_set_type()
104 irq_hw_number_t hwirq; in ls_extirq_domain_alloc() local
109 hwirq = fwspec->param[0]; in ls_extirq_domain_alloc()
110 if (hwirq >= priv->nirq) in ls_extirq_domain_alloc()
113 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip, in ls_extirq_domain_alloc()
116 return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]); in ls_extirq_domain_alloc()
141 u32 hwirq, intsize, j; in ls_extirq_parse_map() local
145 hwirq = be32_to_cpup(map); in ls_extirq_parse_map()
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H A Dirq-sifive-plic.c76 /* device interrupts + 1 to compensate for the reserved hwirq 0 */
108 static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable) in __plic_toggle() argument
111 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
112 int group = hwirq / 32; in __plic_toggle()
126 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) in plic_toggle() argument
131 __plic_toggle(handler, hwirq, enable); in plic_toggle()
143 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
151 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_unmask()
158 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_mask()
178 reg = handler->enable_base + (d->hwirq / 32) * sizeof(u32); in plic_irq_eoi()
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H A Dirq-ti-sci-inta.c30 #define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \ argument
32 #define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK)) argument
47 * hwirq and vint bit.
49 * @hwirq: Hwirq of the incoming interrupt
54 u32 hwirq; member
118 static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, u32 hwirq) in ti_sci_inta_get_dev_id() argument
120 u16 dev_id = HWIRQ_TO_DEVID(hwirq); in ti_sci_inta_get_dev_id()
163 generic_handle_domain_irq(domain, vint_desc->events[bit].hwirq); in ti_sci_inta_irq_handler()
169 * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
275 * @hwirq: hwirq of the input event
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H A Dirq-sni-exiu.c44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
89 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
91 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
103 val |= BIT(d->hwirq); in exiu_irq_set_type()
105 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
110 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
113 val |= BIT(d->hwirq); in exiu_irq_set_type()
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H A Dirq-xilinx-intc.c67 unsigned long mask = BIT(d->hwirq); in intc_enable_or_unmask()
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
86 xintc_write(irqc, CIE, BIT(d->hwirq)); in intc_disable_or_mask()
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
94 xintc_write(irqc, IAR, BIT(d->hwirq)); in intc_ack()
100 unsigned long mask = BIT(d->hwirq); in intc_mask_ack()
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
145 u32 hwirq = xintc_read(irqc, IVR); in xil_intc_irq_handler() local
147 if (hwirq == -1U) in xil_intc_irq_handler()
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H A Dirq-sg2042-msi.c63 static void sg204x_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hwirq, int num_req) in sg204x_msi_free_hwirq() argument
66 bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req)); in sg204x_msi_free_hwirq()
72 int bit_off = d->hwirq; in sg2042_msi_irq_ack()
85 msg->data = 1 << d->hwirq; in sg2042_msi_irq_compose_msi_msg()
105 writel(0, (u32 __iomem *)data->reg_clr + d->hwirq); in sg2044_msi_irq_ack()
112 phys_addr_t doorbell = data->doorbell_addr + 4 * (d->hwirq / 32); in sg2044_msi_irq_compose_msi_msg()
116 msg->data = d->hwirq % 32; in sg2044_msi_irq_compose_msi_msg()
132 static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq) in sg204x_msi_parent_domain_alloc() argument
141 fwspec.param[0] = data->irq_first + hwirq; in sg204x_msi_parent_domain_alloc()
156 int hwirq, err, i; in sg204x_msi_middle_domain_alloc() local
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H A Dirq-mbigen.c67 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) in get_mbigen_vec_reg() argument
71 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
72 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_vec_reg()
73 pin = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_vec_reg()
79 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, in get_mbigen_type_reg() argument
84 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
85 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_type_reg()
86 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_type_reg()
95 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, in get_mbigen_clear_reg() argument
98 unsigned int ofst = (hwirq / 32) * 4; in get_mbigen_clear_reg()
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H A Dirq-lpc32xx.c49 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_mask()
58 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_unmask()
67 u32 mask = BIT(d->hwirq); in lpc32xx_irq_ack()
75 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_set_type()
143 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; in lpc32xx_handle_irq() local
145 while (hwirq) { in lpc32xx_handle_irq()
146 irq = __ffs(hwirq); in lpc32xx_handle_irq()
147 hwirq &= ~BIT(irq); in lpc32xx_handle_irq()
156 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; in lpc32xx_sic_handler() local
160 while (hwirq) { in lpc32xx_sic_handler()
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/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_ht_magic_addr() argument
75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_u4_magic_addr() argument
97 return 0xf8004000 | (hwirq << 4); in find_u4_magic_addr()
105 irq_hw_number_t hwirq; in u3msi_teardown_msi_irqs() local
108 hwirq = virq_to_hw(entry->irq); in u3msi_teardown_msi_irqs()
112 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); in u3msi_teardown_msi_irqs()
122 int hwirq; in u3msi_setup_msi_irqs() local
136 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); in u3msi_setup_msi_irqs()
137 if (hwirq < 0) { in u3msi_setup_msi_irqs()
138 pr_debug("u3msi: failed allocating hwirq\n"); in u3msi_setup_msi_irqs()
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H A Dfsl_msi.c8 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
72 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); in fsl_msi_print_chip() local
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
109 int rc, hwirq; in fsl_msi_init_allocator() local
120 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++) in fsl_msi_init_allocator()
121 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq); in fsl_msi_init_allocator()
130 irq_hw_number_t hwirq; in fsl_teardown_msi_irqs() local
133 hwirq = virq_to_hw(entry->irq); in fsl_teardown_msi_irqs()
138 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); in fsl_teardown_msi_irqs()
142 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, in fsl_compose_msi_msg() argument
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/linux/arch/powerpc/platforms/85xx/
H A Dsocrates_fpga_pic.c110 unsigned int irq_line, hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_ack() local
113 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_ack()
117 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_ack()
125 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask() local
129 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask()
133 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask()
141 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask_ack() local
145 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask_ack()
149 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask_ack()
150 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_mask_ack()
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/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c61 irq_hw_number_t hwirq; in pasemi_msi_teardown_msi_irqs() local
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
70 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK); in pasemi_msi_teardown_msi_irqs()
79 int hwirq; in pasemi_msi_setup_msi_irqs() local
95 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, in pasemi_msi_setup_msi_irqs()
97 if (hwirq < 0) { in pasemi_msi_setup_msi_irqs()
98 pr_debug("pasemi_msi: failed allocating hwirq\n"); in pasemi_msi_setup_msi_irqs()
99 return hwirq; in pasemi_msi_setup_msi_irqs()
102 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); in pasemi_msi_setup_msi_irqs()
104 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n", in pasemi_msi_setup_msi_irqs()
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/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c145 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
147 return (hwirq % msi->nr_irqs); in hwirq_to_group()
151 unsigned long hwirq) in iproc_msi_addr_offset() argument
154 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
156 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
196 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
198 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
202 unsigned long hwirq) in hwirq_to_canonical_hwirq()
204 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
215 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
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/linux/arch/arm/mach-imx/
H A Dgpc.c91 unsigned int idx = d->hwirq / 32; in imx_gpc_irq_set_wake()
94 mask = 1 << d->hwirq % 32; in imx_gpc_irq_set_wake()
125 void imx_gpc_hwirq_unmask(unsigned int hwirq) in imx_gpc_hwirq_unmask() argument
130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
132 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
136 void imx_gpc_hwirq_mask(unsigned int hwirq) in imx_gpc_hwirq_mask() argument
141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
143 val |= 1 << (hwirq % 32); in imx_gpc_hwirq_mask()
149 imx_gpc_hwirq_unmask(d->hwirq); in imx_gpc_irq_unmask()
155 imx_gpc_hwirq_mask(d->hwirq); in imx_gpc_irq_mask()
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/linux/drivers/gpio/
H A Dgpio-lpc18xx.c78 irq_hw_number_t hwirq = irqd_to_hwirq(d); in lpc18xx_gpio_pin_ic_mask() local
83 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
87 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
94 gpiochip_disable_irq(ic->gpio, hwirq); in lpc18xx_gpio_pin_ic_mask()
101 irq_hw_number_t hwirq = irqd_to_hwirq(d); in lpc18xx_gpio_pin_ic_unmask() local
103 gpiochip_enable_irq(ic->gpio, hwirq); in lpc18xx_gpio_pin_ic_unmask()
108 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
112 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
128 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_eoi()
143 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); in lpc18xx_gpio_pin_ic_set_type()
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H A Dgpio-xgene-sb.c48 * @parent_irq_base: Start parent HWIRQ
59 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start) argument
79 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq); in xgene_gpio_sb_irq_set_type()
98 d->hwirq, lvl_type); in xgene_gpio_sb_irq_set_type()
113 gpiochip_disable_irq(&priv->chip.gc, d->hwirq); in xgene_gpio_sb_irq_mask()
120 gpiochip_enable_irq(&priv->chip.gc, d->hwirq); in xgene_gpio_sb_irq_unmask()
156 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); in xgene_gpio_sb_domain_activate()
176 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); in xgene_gpio_sb_domain_deactivate()
185 unsigned long *hwirq, in xgene_gpio_sb_domain_translate() argument
193 *hwirq = fwspec->param[0]; in xgene_gpio_sb_domain_translate()
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/linux/drivers/mailbox/
H A Dqcom-ipcc.c77 u32 hwirq; in qcom_ipcc_irq_fn() local
81 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
82 if (hwirq == IPCC_NO_PENDING_IRQ) in qcom_ipcc_irq_fn()
85 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
86 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
96 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); in qcom_ipcc_mask_irq() local
98 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
104 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); in qcom_ipcc_unmask_irq() local
106 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); in qcom_ipcc_unmask_irq()
152 u32 hwirq; in qcom_ipcc_mbox_send_data() local
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/linux/drivers/pinctrl/mediatek/
H A Dmtk-eint.c108 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) in mtk_eint_flip_edge() argument
112 unsigned int mask = BIT(eint->pins[hwirq].index & 0x1f); in mtk_eint_flip_edge()
113 unsigned int port = (eint->pins[hwirq].index >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
114 void __iomem *reg = eint->base[eint->pins[hwirq].instance] + (port << 2); in mtk_eint_flip_edge()
116 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
127 hwirq); in mtk_eint_flip_edge()
136 unsigned int idx = eint->pins[d->hwirq].index; in mtk_eint_mask()
137 unsigned int inst = eint->pins[d->hwirq].instance; in mtk_eint_mask()
139 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
150 unsigned int idx = eint->pins[d->hwirq].index; in mtk_eint_unmask()
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/linux/drivers/vfio/platform/
H A Dvfio_platform_irq.c25 disable_irq_nosync(irq_ctx->hwirq); in vfio_platform_mask()
85 enable_irq(irq_ctx->hwirq); in vfio_platform_unmask()
161 disable_irq_nosync(irq_ctx->hwirq); in vfio_automasked_irq_handler()
189 disable_irq(irq->hwirq); in vfio_set_trigger()
210 enable_irq(irq->hwirq); in vfio_set_trigger()
241 handler(irq->hwirq, irq); in vfio_platform_set_irq_trigger()
247 handler(irq->hwirq, irq); in vfio_platform_set_irq_trigger()
300 int hwirq = vdev->get_irq(vdev, i); in vfio_platform_irq_init() local
303 if (hwirq < 0) { in vfio_platform_irq_init()
312 if (irq_get_trigger_type(hwirq) & IRQ_TYPE_LEVEL_MASK) { in vfio_platform_irq_init()
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/linux/arch/powerpc/platforms/44x/
H A Dhsta_msi.c42 int irq, hwirq; in hsta_setup_msi_irqs() local
59 hwirq = ppc4xx_hsta_msi.irq_map[irq]; in hsta_setup_msi_irqs()
60 if (!hwirq) { in hsta_setup_msi_irqs()
76 pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq, in hsta_setup_msi_irqs()
79 if (irq_set_msi_desc(hwirq, entry)) { in hsta_setup_msi_irqs()
81 "%s: Invalid hwirq %d specified in device tree\n", in hsta_setup_msi_irqs()
82 __func__, hwirq); in hsta_setup_msi_irqs()
86 pci_write_msi_msg(hwirq, &msg); in hsta_setup_msi_irqs()
92 static int hsta_find_hwirq_offset(int hwirq) in hsta_find_hwirq_offset() argument
96 /* Find the offset given the hwirq */ in hsta_find_hwirq_offset()
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