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Searched full:hwirq (Results 1 – 25 of 322) sorted by relevance

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/linux/drivers/irqchip/
H A Dirq-sp7021-intc.c81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value) in sp_intc_assign_bit() argument
87 offset = (hwirq / 32) * 4; in sp_intc_assign_bit()
93 mask |= BIT(hwirq % 32); in sp_intc_assign_bit()
95 mask &= ~BIT(hwirq % 32); in sp_intc_assign_bit()
102 u32 hwirq = d->hwirq; in sp_intc_ack_irq() local
104 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND in sp_intc_ack_irq()
105 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW)); in sp_intc_ack_irq()
106 ASSIGN_STATE(hwirq, _IS_ACTIVE, true); in sp_intc_ack_irq()
109 sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1); in sp_intc_ack_irq()
114 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0); in sp_intc_mask_irq()
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H A Dirq-renesas-rzg2l.c93 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) in rzg2l_clear_irq_int() argument
95 unsigned int hw_irq = hwirq - IRQC_IRQ_START; in rzg2l_clear_irq_int()
116 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) in rzg2l_clear_tint_int() argument
118 u32 bit = BIT(hwirq - IRQC_TINT_START); in rzg2l_clear_tint_int()
147 unsigned int hwirq) in rzfive_irqc_mask_irq_interrupt() argument
149 u32 bit = BIT(hwirq - IRQC_IRQ_START); in rzfive_irqc_mask_irq_interrupt()
155 unsigned int hwirq) in rzfive_irqc_unmask_irq_interrupt() argument
157 u32 bit = BIT(hwirq - IRQC_IRQ_START); in rzfive_irqc_unmask_irq_interrupt()
163 unsigned int hwirq) in rzfive_irqc_mask_tint_interrupt() argument
165 u32 bit = BIT(hwirq - IRQC_TINT_START); in rzfive_irqc_mask_tint_interrupt()
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H A Dirq-mchp-eic.c51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
105 eic->wakeup_source |= BIT(d->hwirq); in mchp_eic_irq_set_wake()
107 eic->wakeup_source &= ~BIT(d->hwirq); in mchp_eic_irq_set_wake()
114 unsigned int hwirq; in mchp_eic_irq_suspend() local
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H A Dirq-mmp.c71 int hwirq; in icu_mask_ack_irq() local
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
95 int hwirq; in icu_mask_irq() local
98 hwirq = d->irq - data->virq_base; in icu_mask_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
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H A Dirq-mvebu-sei.c61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
63 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
76 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
84 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
90 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
146 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
201 unsigned long *hwirq, in mvebu_sei_ap_translate() argument
204 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
215 unsigned long hwirq; in mvebu_sei_ap_alloc() local
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H A Dirq-pruss-intc.c173 * @hwirq: the system event number
178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_map() argument
186 intc->event_channel[hwirq].ref_count++; in pruss_intc_map()
188 ch = intc->event_channel[hwirq].value; in pruss_intc_map()
191 pruss_intc_update_cmr(intc, hwirq, ch); in pruss_intc_map()
193 reg_idx = hwirq / 32; in pruss_intc_map()
194 val = BIT(hwirq % 32); in pruss_intc_map()
208 hwirq, ch, host); in pruss_intc_map()
216 * @hwirq: the system event number
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_unmap() argument
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H A Dirq-partition-percpu.c26 unsigned int cpu, unsigned int hwirq) in partition_check_cpu() argument
28 return cpumask_test_cpu(cpu, &part->parts[hwirq].mask); in partition_check_cpu()
37 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_mask()
48 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_unmask()
61 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_set_irqchip_state()
76 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_get_irqchip_state()
101 seq_printf(p, "%5s-%lu", chip->name, data->hwirq); in partition_irq_print_chip()
118 int hwirq; in partition_handle_irq() local
122 for_each_set_bit(hwirq, part->bitmap, part->nr_parts) { in partition_handle_irq()
123 if (partition_check_cpu(part, cpu, hwirq)) in partition_handle_irq()
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H A Dirq-ls-extirq.c57 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type() local
61 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
63 mask = 1U << hwirq; in ls_extirq_set_type()
104 irq_hw_number_t hwirq; in ls_extirq_domain_alloc() local
109 hwirq = fwspec->param[0]; in ls_extirq_domain_alloc()
110 if (hwirq >= priv->nirq) in ls_extirq_domain_alloc()
113 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip, in ls_extirq_domain_alloc()
116 return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]); in ls_extirq_domain_alloc()
141 u32 hwirq, intsize, j; in ls_extirq_parse_map() local
145 hwirq = be32_to_cpup(map); in ls_extirq_parse_map()
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H A Dirq-sifive-plic.c97 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) in __plic_toggle() argument
99 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); in __plic_toggle()
100 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
108 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) in plic_toggle() argument
113 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
125 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
133 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_unmask()
140 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_mask()
159 plic_toggle(handler, d->hwirq, 1); in plic_irq_eoi()
160 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); in plic_irq_eoi()
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H A Dirq-or1k-pic.c28 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask()
33 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq)); in or1k_pic_unmask()
38 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_ack()
43 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask_ack()
44 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_mask_ack()
55 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_ack()
60 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
61 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
102 int hwirq; in pic_get_irq() local
104 hwirq = ffs(mfspr(SPR_PICSR) >> first); in pic_get_irq()
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H A Dirq-sni-exiu.c44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
89 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
91 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
103 val |= BIT(d->hwirq); in exiu_irq_set_type()
105 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
110 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
113 val |= BIT(d->hwirq); in exiu_irq_set_type()
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H A Dirq-riscv-intc.c54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
65 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
71 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
75 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
77 if (d->hwirq < ANDES_SLI_CAUSE_BASE) in andes_intc_irq_mask()
85 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_unmask()
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H A Dirq-mvebu-odmi.c59 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
62 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
63 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
87 unsigned int hwirq, odmin; in odmi_irq_domain_alloc() local
91 hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count); in odmi_irq_domain_alloc()
92 if (hwirq >= NODMIS_PER_FRAME * odmis_count) { in odmi_irq_domain_alloc()
97 __set_bit(hwirq, odmis_bm); in odmi_irq_domain_alloc()
100 odmi = &odmis[hwirq >> NODMIS_SHIFT]; in odmi_irq_domain_alloc()
101 odmin = hwirq & NODMIS_MASK; in odmi_irq_domain_alloc()
122 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, in odmi_irq_domain_alloc()
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H A Dirq-xilinx-intc.c67 unsigned long mask = BIT(d->hwirq); in intc_enable_or_unmask()
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
86 xintc_write(irqc, CIE, BIT(d->hwirq)); in intc_disable_or_mask()
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
94 xintc_write(irqc, IAR, BIT(d->hwirq)); in intc_ack()
100 unsigned long mask = BIT(d->hwirq); in intc_mask_ack()
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
145 u32 hwirq = xintc_read(irqc, IVR); in xil_intc_irq_handler() local
147 if (hwirq == -1U) in xil_intc_irq_handler()
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H A Dirq-mbigen.c81 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) in get_mbigen_vec_reg() argument
85 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
86 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_vec_reg()
87 pin = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_vec_reg()
92 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, in get_mbigen_type_reg() argument
97 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
98 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_type_reg()
99 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_type_reg()
107 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, in get_mbigen_clear_reg() argument
110 unsigned int ofst = (hwirq / 32) * 4; in get_mbigen_clear_reg()
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/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_ht_magic_addr() argument
75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_u4_magic_addr() argument
97 return 0xf8004000 | (hwirq << 4); in find_u4_magic_addr()
105 irq_hw_number_t hwirq; in u3msi_teardown_msi_irqs() local
108 hwirq = virq_to_hw(entry->irq); in u3msi_teardown_msi_irqs()
112 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); in u3msi_teardown_msi_irqs()
122 int hwirq; in u3msi_setup_msi_irqs() local
136 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); in u3msi_setup_msi_irqs()
137 if (hwirq < 0) { in u3msi_setup_msi_irqs()
138 pr_debug("u3msi: failed allocating hwirq\n"); in u3msi_setup_msi_irqs()
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/linux/arch/powerpc/platforms/powernv/
H A Dpci-cxl.c43 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); in pnv_cxl_alloc_hwirqs() local
45 if (hwirq < 0) { in pnv_cxl_alloc_hwirqs()
50 return phb->msi_base + hwirq; in pnv_cxl_alloc_hwirqs()
54 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) in pnv_cxl_release_hwirqs() argument
59 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); in pnv_cxl_release_hwirqs()
68 int i, hwirq; in pnv_cxl_release_hwirq_ranges() local
76 hwirq = irqs->offset[i] - phb->msi_base; in pnv_cxl_release_hwirq_ranges()
77 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, in pnv_cxl_release_hwirq_ranges()
88 int i, hwirq, try; in pnv_cxl_alloc_hwirq_ranges() local
96 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); in pnv_cxl_alloc_hwirq_ranges()
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/linux/Documentation/core-api/irq/
H A Dirq-domain.rst29 the controller-local IRQ (hwirq) number into the Linux IRQ number
32 The irq_domain library adds mapping between hwirq and IRQ numbers on
38 structure to hwirq numbers (Device Tree and ACPI GSI so far), and can
51 between hwirq and IRQ numbers. Mappings are added to the irq_domain
53 hwirq number as arguments. If a mapping for the hwirq doesn't already
55 the hwirq, and call the .map() callback so the driver can perform any
62 for a given domain and hwirq number, and NULL if there was no
65 hwirq number, and 0 if there was no mapping
69 domain and a hwirq number
79 needs to know the associated hwirq number (such as in the irq_chip
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/linux/arch/powerpc/platforms/85xx/
H A Dsocrates_fpga_pic.c110 unsigned int irq_line, hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_ack() local
113 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_ack()
117 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_ack()
125 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask() local
129 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask()
133 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask()
141 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask_ack() local
145 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask_ack()
149 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask_ack()
150 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_mask_ack()
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/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c61 irq_hw_number_t hwirq; in pasemi_msi_teardown_msi_irqs() local
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
70 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK); in pasemi_msi_teardown_msi_irqs()
79 int hwirq; in pasemi_msi_setup_msi_irqs() local
95 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, in pasemi_msi_setup_msi_irqs()
97 if (hwirq < 0) { in pasemi_msi_setup_msi_irqs()
98 pr_debug("pasemi_msi: failed allocating hwirq\n"); in pasemi_msi_setup_msi_irqs()
99 return hwirq; in pasemi_msi_setup_msi_irqs()
102 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); in pasemi_msi_setup_msi_irqs()
104 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n", in pasemi_msi_setup_msi_irqs()
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/linux/drivers/pinctrl/mediatek/
H A Dmtk-eint.c101 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) in mtk_eint_flip_edge() argument
105 u32 mask = BIT(hwirq & 0x1f); in mtk_eint_flip_edge()
106 u32 port = (hwirq >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
109 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
120 hwirq); in mtk_eint_flip_edge()
129 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_mask()
130 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
133 eint->cur_mask[d->hwirq >> 5] &= ~mask; in mtk_eint_mask()
141 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_unmask()
142 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_unmask()
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/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
148 return (hwirq % msi->nr_irqs); in hwirq_to_group()
152 unsigned long hwirq) in iproc_msi_addr_offset() argument
155 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
157 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
197 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
201 unsigned long hwirq) in hwirq_to_canonical_hwirq()
203 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
214 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
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/linux/kernel/irq/
H A Dirqdomain.c488 * @first_hwirq: first hwirq number to use for the translation. Should normally
614 irq_hw_number_t hwirq) in irq_domain_clear_mapping() argument
621 if (hwirq < domain->revmap_size) in irq_domain_clear_mapping()
622 rcu_assign_pointer(domain->revmap[hwirq], NULL); in irq_domain_clear_mapping()
624 radix_tree_delete(&domain->revmap_tree, hwirq); in irq_domain_clear_mapping()
628 irq_hw_number_t hwirq, in irq_domain_set_mapping() argument
640 if (hwirq < domain->revmap_size) in irq_domain_set_mapping()
641 rcu_assign_pointer(domain->revmap[hwirq], irq_data); in irq_domain_set_mapping()
643 radix_tree_insert(&domain->revmap_tree, hwirq, irq_data); in irq_domain_set_mapping()
649 irq_hw_number_t hwirq; in irq_domain_disassociate() local
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/linux/arch/arm/mach-imx/
H A Dgpc.c91 unsigned int idx = d->hwirq / 32; in imx_gpc_irq_set_wake()
94 mask = 1 << d->hwirq % 32; in imx_gpc_irq_set_wake()
125 void imx_gpc_hwirq_unmask(unsigned int hwirq) in imx_gpc_hwirq_unmask() argument
130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
132 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
136 void imx_gpc_hwirq_mask(unsigned int hwirq) in imx_gpc_hwirq_mask() argument
141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
143 val |= 1 << (hwirq % 32); in imx_gpc_hwirq_mask()
149 imx_gpc_hwirq_unmask(d->hwirq); in imx_gpc_irq_unmask()
155 imx_gpc_hwirq_mask(d->hwirq); in imx_gpc_irq_mask()
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/linux/drivers/misc/cxl/
H A Dirq.c174 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); in cxl_irq_afu() local
192 irq_off = hwirq - ctx->irqs.offset[r]; in cxl_irq_afu()
201 WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n", in cxl_irq_afu()
202 ctx->pe, irq, hwirq); in cxl_irq_afu()
206 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); in cxl_irq_afu()
207 pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n", in cxl_irq_afu()
208 afu_irq, ctx->pe, irq, hwirq); in cxl_irq_afu()
224 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, in cxl_map_irq() argument
231 virq = irq_create_mapping(NULL, hwirq); in cxl_map_irq()
238 cxl_ops->setup_irq(adapter, hwirq, virq); in cxl_map_irq()
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