54 	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)  in riscv_intc_irq_mask()
55 		csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));  in riscv_intc_irq_mask()
57 		csr_clear(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_mask()
62 	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)  in riscv_intc_irq_unmask()
63 		csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));  in riscv_intc_irq_unmask()
65 		csr_set(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_unmask()
71 	 * Andes specific S-mode local interrupt causes (hwirq)  in andes_intc_irq_mask()
75 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_mask()
77 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_mask()
85 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_unmask()
87 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_unmask()
124 				 irq_hw_number_t hwirq)  in riscv_intc_domain_map()  argument
129 	irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,  in riscv_intc_domain_map()
140 	irq_hw_number_t hwirq;  in riscv_intc_domain_alloc()  local
144 	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);  in riscv_intc_domain_alloc()
149 	 * Only allow hwirq for which we have corresponding standard or  in riscv_intc_domain_alloc()
152 	if (hwirq >= riscv_intc_nr_irqs &&  in riscv_intc_domain_alloc()
153 	    (hwirq < riscv_intc_custom_base ||  in riscv_intc_domain_alloc()
154 	     hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))  in riscv_intc_domain_alloc()
158 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);  in riscv_intc_domain_alloc()