50 static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value)  in msix_cfg_set()  argument
52 	iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq));  in msix_cfg_set()
55 static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value)  in msix_cfg_clr()  argument
57 	iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq));  in msix_cfg_clr()
63 	struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];  in rp1_mask_irq()
71 	struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];  in rp1_unmask_irq()
79 	unsigned int hwirq = (unsigned int)irqd->hwirq;  in rp1_irq_set_type()  local
83 		dev_dbg(&rp1->pdev->dev, "MSIX IACK EN for IRQ %u\n", hwirq);  in rp1_irq_set_type()
84 		msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN);  in rp1_irq_set_type()
85 		rp1->level_triggered_irq[hwirq] = true;  in rp1_irq_set_type()
88 		msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN);  in rp1_irq_set_type()
89 		rp1->level_triggered_irq[hwirq] = false;  in rp1_irq_set_type()
107 	unsigned int hwirq = desc->irq_data.hwirq & RP1_HW_IRQ_MASK;  in rp1_chained_handle_irq()  local
114 	virq = irq_find_mapping(rp1->domain, hwirq);  in rp1_chained_handle_irq()
116 	if (rp1->level_triggered_irq[hwirq])  in rp1_chained_handle_irq()
117 		msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK);  in rp1_chained_handle_irq()
128 	unsigned long hwirq;  in rp1_irq_xlate()  local
133 				       &hwirq, out_type);  in rp1_irq_xlate()
137 	pcie_irq = pci_irq_vector(rp1->pdev, hwirq);  in rp1_irq_xlate()
139 	rp1->pcie_irqds[hwirq] = pcie_irqd;  in rp1_irq_xlate()
140 	*out_hwirq = hwirq;  in rp1_irq_xlate()
150 	msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);  in rp1_irq_activate()
159 	msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);  in rp1_irq_deactivate()