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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
19 - nvidia,tegra264-pmc
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/linux/sound/hda/codecs/hdmi/
H A Dtegrahdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Nvidia Tegra HDMI codec support
23 * accessed using vendor-defined verbs. These registers can be used for
24 * interoperability between the HDA and HDMI drivers.
31 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
33 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
38 * +---------+-------+--------+--------+
40 * +-----------------------------------|
45 * trigger to hdmi.
64 * the format is invalidated so that the HDMI codec can be disabled.
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
49 (enc10->link_regs->index)
177 enable ? "Enabling" : "Disabling", enc->id.enum_id); in enc2_fec_set_enable()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
146 enum port port = encoder->port; in intel_cx0_bus_reset()
155 drm_err_once(display->drm, in intel_cx0_bus_reset()
168 enum port port = encoder->port; in intel_cx0_wait_for_ack()
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/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
59 #include <dt-bindings/gpio/tegra186-gpio.h>
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
707 // =3: HDMI encoder
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/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
714 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
795 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
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