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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/linux/include/sound/
H A Dhda_verbs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * HD-audio codec verbs
59 /* f10-f1a: GPIO */
162 #define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
163 #define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
164 #define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
242 * (for DP1.2 MST)
245 #define AC_UNSOL_RES_IA (1<<2) /* Inactive (for DP1.2 MST) */
246 #define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
263 /* Note: The same bit as LR_SWAP is newly defined as HDMI capability
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/linux/drivers/gpu/drm/amd/display/modules/info_packet/
H A Dinfo_packet.c41 //04h = 3D stereo + PSR/PSR2 + Y-coordinate.
43 //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format
72 //0: Periodic pseudo-static EM Data Set
85 //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
86 //2: This EM Data Set is defined by CTA-861-G
99 //PB7-27 (20 bytes):
144 …if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FOR… in mod_build_vsc_infopacket()
149 /* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */ in mod_build_vsc_infopacket()
150 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) in mod_build_vsc_infopacket()
152 else if (stream->link->replay_settings.config.replay_supported) in mod_build_vsc_infopacket()
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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H A Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
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/linux/sound/pci/hda/
H A Dpatch_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
172 /* hdmi interrupt trigger control flag for Nvidia codec */
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/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c77 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
231 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
232 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
243 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
244 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
256 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
257 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
279 * - Clock recovery vs. channel equalization
280 * - DPRX vs. LTTPR
281 * - 128b/132b vs. 8b/10b
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/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
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/linux/sound/soc/codecs/
H A Dhdac_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * hdac_hdmi.c - ASoc HDA-HDMI codec driver for Intel platforms
5 * Copyright (C) 2014-2015 Intel Corp
17 #include <linux/hdmi.h>
109 unsigned char chmap[8]; /* ALSA API channel-map */
142 #define hdev_to_hdmi_priv(_hdev) dev_get_drvdata(&(_hdev)->dev)
145 hdac_hdmi_get_pcm_from_cvt(struct hdac_hdmi_priv *hdmi, in hdac_hdmi_get_pcm_from_cvt() argument
150 list_for_each_entry(pcm, &hdmi->pcm_list, head) { in hdac_hdmi_get_pcm_from_cvt()
151 if (pcm->cvt == cvt) in hdac_hdmi_get_pcm_from_cvt()
161 struct hdac_device *hdev = port->pin->hdev; in hdac_hdmi_jack_report()
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
707 // =3: HDMI encoder
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
24 #address-cells = <1>;
25 #size-cells = <0>;
31 remote-endpoint = <&xbar_i2s1_ep>;
39 dai-format = "i2s";
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_hotplug_irq.c1 // SPDX-License-Identifier: MIT
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_init_pins()
141 hpd->hpd = hpd_status_g4x; in intel_hpd_init_pins()
143 hpd->hpd = hpd_status_i915; in intel_hpd_init_pins()
148 hpd->hpd = hpd_xelpdp; in intel_hpd_init_pins()
150 hpd->hpd = hpd_gen11; in intel_hpd_init_pins()
152 hpd->hpd = hpd_bxt; in intel_hpd_init_pins()
154 hpd->hpd = NULL; /* no north HPD on SKL */ in intel_hpd_init_pins()
156 hpd->hpd = hpd_bdw; in intel_hpd_init_pins()
158 hpd->hpd = hpd_ivb; in intel_hpd_init_pins()
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H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
36 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
65 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
75 struct drm_i915_private *i915 = to_i915(display->drm); in assert_dc_off()
79 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
89 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
106 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
118 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
131 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
138 enum port port = encoder->port; in intel_cx0_bus_reset()
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H A Dintel_ddi_buf_trans.c1 // SPDX-License-Identifier: MIT
14 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
16 * automatically adapt to HDMI connections as well
399 /* BSpec has 2 recommended values - entries 0 and 8.
419 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
475 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
593 /* Voltage swing pre-emphasis */
612 /* Voltage swing pre-emphasis */
631 /* HDMI Preset VS Pre-emph */
637 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 auddsm_pins: auddsm-pins {
30 /omit-if-no-ref/
31 bt1120_pins: bt1120-pins {
71 /omit-if-no-ref/
72 can0m0_pins: can0m0-pins {
80 /omit-if-no-ref/
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c57 link->ctx->logger
109 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && in is_dp_active_dongle()
110 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); in is_dp_active_dongle()
115 return link->dpcd_caps.is_branch_dev; in is_dp_branch_device()
133 return -1; in translate_dpcd_max_bpc()
187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
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/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c31 * TODO - The reason link owns stream's dpms programming sequence is
83 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
89 dp_retrieve_lttpr_cap(dc->links[i]); in link_blank_all_dp_displays()
91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in link_blank_all_dp_displays()
95 link_blank_dp_stream(dc->links[i], true); in link_blank_all_dp_displays()
106 for (i = 0; i < dc->link_count; i++) { in link_blank_all_edp_displays()
107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || in link_blank_all_edp_displays()
108 (!dc->links[i]->edp_sink_present)) in link_blank_all_edp_displays()
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/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
897 /* Audio - I2S */
904 /* SPI Pre-Ratio */
1227 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1229 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1438 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
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