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/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
26 struct member has a short description which is marked with an [XXX]
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
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/linux/Documentation/devicetree/bindings/mtd/
H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
35 interesting ways, sometimes with registers that lump multiple NAND-related
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H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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/linux/drivers/mtd/nand/raw/
H A Dnand_micron.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
14 * Special Micron status bit 3 indicates that the block has been
15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
24 * ----- ----- ----- -----------
27 * 0 1 0 4 - 6 errors corrected, recommend rewrite
29 * 1 0 0 1 - 3 errors corrected
31 * 1 1 0 7 - 8 errors corrected, recommend rewrite
66 struct micron_on_die_ecc ecc; member
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "diges
955 marvell_nfc_check_empty_chunk(struct nand_chip * chip,u8 * data,int data_len,u8 * spare,int spare_len,u8 * ecc,int ecc_len,unsigned int * max_bitflips) marvell_nfc_check_empty_chunk() argument
2245 marvell_nand_hw_ecc_controller_init(struct mtd_info * mtd,struct nand_ecc_ctrl * ecc) marvell_nand_hw_ecc_controller_init() argument
2319 marvell_nand_ecc_init(struct mtd_info * mtd,struct nand_ecc_ctrl * ecc) marvell_nand_ecc_init() argument
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H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enabl
405 lpc32xx_slc_ecc_copy(uint8_t * spare,const uint32_t * ecc,int count) lpc32xx_slc_ecc_copy() argument
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H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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H A Dfsl_elbc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
9 * Roy Zang <tie-fei.zang@freescale.com>
66 /* These map to the positions used by the FCM hardware ECC generator */
74 if (section >= chip->ecc.steps) in fsl_elbc_ooblayout_ecc()
75 return -ERANGE; in fsl_elbc_ooblayout_ecc()
77 oobregion->offset = (16 * section) + 6; in fsl_elbc_ooblayout_ecc()
78 if (priv->fmr & FMR_ECCM) in fsl_elbc_ooblayout_ecc()
79 oobregion->offset += 2; in fsl_elbc_ooblayout_ecc()
81 oobregion->length = chip->ecc.bytes; in fsl_elbc_ooblayout_ecc()
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H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
15 * - Untested on MPC5125 and M54418.
16 * - DMA and pipelining not used.
17 * - 2K pages or less.
18 * - HW ECC: Only 2K page with 64+ OOB.
19 * - HW ECC: Only 24 and 32-bit error correction implemented.
67 #define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1)
76 /* NFC ECC mode define */
136 * ECC status - seems to consume 8 bytes (double word). The documented
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/linux/fs/ocfs2/
H A Dblockcheck.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Checksum and ECC codes for the OCFS2 userspace library.
39 * power-of-two bits for parity, the data bit number and the code bit
42 * Recall that bit numbers in hamming code are 1-based. This function
43 * takes the 0-based data bit from the caller.
59 * Data bits are 0-based, but we're talking code bits, which in calc_code_bit()
60 * are 1-based. in calc_code_bit()
105 * 1-based array, but C uses 0-based. So 'i' is for C, and 'b' is in ocfs2_hamming_encode()
164 * If the bit to fix has an hweight of 1, it's a parity bit. One in ocfs2_hamming_fix()
235 debugfs_remove_recursive(stats->b_debug_dir); in ocfs2_blockcheck_debug_remove()
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/linux/drivers/mtd/nand/
H A Decc-realtek.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Realtek hardware ECC engine in RTL93xx SoCs
7 #include <linux/dma-mapping.h>
14 * The Realtek ECC engine has two operation modes.
16 * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes
17 * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
20 * are only two known devices in the wild that have NAND flash and make use of this ECC engine
25 * This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the
28 * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC!
29 * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC!
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H A Decc-sw-bch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
33 for (i = 0; i < engine_conf->code_size; i++) in nand_ecc_sw_bch_calculate()
34 code[i] ^= engine_conf->eccmask[i]; in nand_ecc_sw_bch_calculate()
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/linux/arch/sparc/include/asm/
H A Dchafsr.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * ch --> cheetah
10 * ch+ --> cheetah plus
11 * jp --> jalapeno
15 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
33 /* Hardware corrected E-cache Tag ECC error */
38 /* SW handled correctable E-cache Tag ECC error */
43 /* Uncorrectable E-cache Tag ECC error */
48 /* Uncorrectable system bus data ECC error due to prefetch
64 * This bit is not set when multiple ECC errors happen within a single
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/linux/drivers/edac/
H A Daltera_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
12 #include <linux/firmware/intel/stratix10-smc.h>
17 #include <linux/mfd/altera-sysmgr.h>
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
85 const struct altr_sdram_prv_data *priv = drvdata->data; in altr_sdram_mc_err_handler()
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); in altr_sdram_mc_err_handler()
90 if (status & priv->ecc_stat_ue_mask) { in altr_sdram_mc_err_handler()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
17 16-bits or 32-bits or 64-bits wide.
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
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H A Dxlnx,versal-net-ddrmc5.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
15 has an optional ECC support which correct single bit ECC errors and detect
16 double bit ECC errors. It also has support for reporting other errors like
17 MMCM (Mixed-Mode Clock Manager) errors and General software errors.
21 const: xlnx,versal-net-ddrmc5
31 - compatible
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H A Dxlnx,zynq-ddrc-a05.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
15 (16-bit) configuration. It is capable of correcting single bit ECC errors
16 and detecting double bit ECC errors.
20 const: xlnx,zynq-ddrc-a05
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H A Dxlnx,versal-ddrmc-edac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
16 which correct single bit ECC errors and detect double bit ECC errors.
20 const: xlnx,versal-ddrmc
24 - description: DDR Memory Controller registers
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/linux/Documentation/firmware-guide/acpi/apei/
H A Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
132 All <field string> description with * has the following format::
139 All <field strings> description with # has the following format::
/linux/include/linux/
H A Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
59 * backlogged) or advancement out of the backlog. If the cmd has
61 * will be -EINPROGRESS. Any other "err" value during callback is
64 * The cmd has been successfully queued if:
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
54 * BIT(6) - ri_tlq_nphdr parity error
55 * BIT(7) - ri_tlq_npdata parity error
56 * BIT(8) - BIT(9) - ri_tlq_cplhdr[0:1] parity error
57 * BIT(10) - BIT(17) - ri_tlq_cpldata[0:7] parity error
58 * BIT(18) - set this bit to 1 to enable logging status to ri_mem_par_err_sts0
59 * BIT(19) - ri_cds_cmd_fifo parity error
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/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-interconnect.json164 "BriefDescription": "BL Ingress Occupancy - DRS",
189 "BriefDescription": "BL Ingress Occupancy - NCB",
214 "BriefDescription": "BL Ingress Occupancy - NCS",
256 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
266 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
276 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
331 …er of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not …
353 "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
363 "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
373 "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
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/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
102 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
103 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
104 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
105 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
115 * fail. Today davinci-pcm is the only user of this driver and
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
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