| /linux/Documentation/devicetree/bindings/iio/addac/ |
| H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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| H A D | adi,ad74413r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
27 - adi,ad74412r
28 - adi,ad74413r
33 '#address-cells':
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| /linux/arch/riscv/kernel/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
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| H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <asm/asm-offsets.h>
18 #include "efi-header.S"
23 * Image header expected by Linux boot-loaders. The image header data
32 c.li s4,-13
42 /* Image load offset (0MB) from start of RAM for M-mode */
46 /* Image load offset(2MB) from start of RAM */
54 .dword _end - _start
63 .word pe_head_start - _start
71 .align 2
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| H A D | kexec_relocate.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
50 * With C-extension, here we get 42 Bytes and the next
57 .align 2
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
62 /* IND_DESTINATION entry ? -> save destination address */
64 beqz t1, 2f
68 2:
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| H A D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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| H A D | sbi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
34 * There is no maximum hartid concept in RISC-V and NR_CPUS must not be in __sbi_v01_cpumask_to_hartmask()
37 * greater than BITS_PER_LONG (32 for RV32 and 64 for RV64). Ideally, SBI v0.2 in __sbi_v01_cpumask_to_hartmask()
53 * sbi_console_putchar() - Writes given character to the console device.
65 * sbi_console_getchar() - Reads a byte from console device.
80 * sbi_shutdown() - Remove all the harts from executing supervisor code.
91 * __sbi_set_timer_v01() - Program the timer for next timer event.
125 /* v0.2 function IDs are equivalent to v0.1 extension IDs */ in __sbi_rfence_v01()
143 result = -EINVAL; in __sbi_rfence_v01()
245 result = -EINVAL; in __sbi_rfence_v02_call()
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | thead,c900-aclint-sswi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ACLINT Supervisor-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
14 supervisor-level IPI functionality for a set of HARTs on a supported
16 HART connected to the SSWI device. See draft specification
17 https://github.com/riscvarchive/riscv-aclint
21 - THEAD C900
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| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
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| /linux/arch/riscv/mm/ |
| H A D | cacheflush.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 if (num_online_cpus() < 2) in flush_icache_all()
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
55 * execution resumes on each hart.
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
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| H A D | context.c | 1 // SPDX-License-Identifier: GPL-2.0
87 /* Mark ASID #0 as used because it is used at boot-time */ in __flush_context()
90 /* Queue a TLB invalidation for each CPU on next context-switch */ in __flush_context()
97 unsigned long cntx = atomic_long_read(&mm->context.id); in __new_context()
115 * re-use it if possible. in __new_context()
150 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
153 * If our active_context is non-zero and the context matches the in set_mm_asid()
159 * - We get a zero back from the cmpxchg and end up waiting on the in set_mm_asid()
163 * - We get a valid context back from the cmpxchg then we continue in set_mm_asid()
178 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
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| /linux/Documentation/arch/riscv/ |
| H A D | cmodx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux
9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
14 -------------------------
17 ---------------------
21 enable or disable the redirection. In the case of RISC-V, 2 instructions,
23 to patch 2 instructions and expect that a concurrent read-side executes them
25 RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
29 preemption, we partially initialize each patchable function entry at boot-time,
36 is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
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| H A D | boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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| /linux/drivers/irqchip/ |
| H A D | irq-riscv-aplic-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
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| H A D | irq-riscv-imsic-state.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
134 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
139 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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| H A D | irq-riscv-imsic-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
23 #include <linux/irqchip/irq-msi-lib.h>
24 #include "irq-riscv-imsic-state.h"
32 global = &imsic->global; in imsic_cpu_page_phys()
33 local = per_cpu_ptr(global->local, cpu); in imsic_cpu_page_phys()
35 if (BIT(global->guest_index_bits) <= guest_index) in imsic_cpu_page_phys()
39 *out_msi_pa = local->msi_pa + (guest_index * IMSIC_MMIO_PAGE_SZ); in imsic_cpu_page_phys()
60 return -ENOENT; in imsic_irq_retrigger()
62 local = per_cpu_ptr(imsic->global.local, vec->cpu); in imsic_irq_retrigger()
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | andestech,plmt0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
11 functionality for a set of HARTs on a RISC-V platform. It has a single
12 fixed-frequency monotonic time counter (MTIME) register and a time compare
13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
17 - Ben Zong-You Xie <ben717@andestech.com>
22 - enum:
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| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| /linux/tools/arch/riscv/include/uapi/asm/ |
| H A D | unistd.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * it under the terms of the GNU General Public License version 2 as
23 #include <asm-generic/unistd.h>
26 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| /linux/tools/testing/selftests/futex/functional/ |
| H A D | futex_requeue_pi_mismatched_ops.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * 2. Attempt to use FUTEX_CMP_REQUEUE_PI on the futex from 1.
9 * 3. The kernel must detect the mismatch and return -EINVAL.
12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
38 child_ret = -errno; in blocking_child()
57 * q->requeue_pi_key and return -EINVAL. If it does not, in TEST()
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| H A D | futex_wait_timeout.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
14 * 2021-Apr-26: More test cases by André Almeida <andrealmeid@collabora.com>
72 to->tv_nsec += timeout_ns; in futex_get_abs_timeout()
74 if (to->tv_nsec >= 1000000000) { in futex_get_abs_timeout()
75 to->tv_sec++; in futex_get_abs_timeout()
76 to->tv_nsec -= 1000000000; in futex_get_abs_timeout()
135 pthread_barrier_init(&barrier, NULL, 2); in TEST()
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| /linux/arch/riscv/purgatory/ |
| H A D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 .align 2
19 mv s0, a0 /* The hartid of the current hart */
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| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| /linux/scripts/gdb/linux/ |
| H A D | cpus.py | 4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
11 # This work is licensed under the terms of the GNU GPL version 2.
27 return gdb.selected_thread().num - 1
36 if cpu == -1:
77 entry = -1
129 super(LxCpus, self).__init__("lx-cpus", gdb.COMMAND_DATA)
142 """Return per-cpu variable.
144 $lx_per_cpu(VAR[, CPU]): Return the per-cpu variable called VAR for the
151 def invoke(self, var, cpu=-1):
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| /linux/tools/testing/selftests/riscv/hwprobe/ |
| H A D | cbo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Run with 'taskset -c <cpu-list> cbo' to only execute hwprobe on a
22 #define MK_CBO(fn) le32_bswap((uint32_t)(fn) << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15)
30 unsigned long *regs = (unsigned long *)&((ucontext_t *)context)->uc_mcontext; in sigill_handler()
44 ".4byte %2\n" \
50 static void cbo_flush(char *base) { cbo_insn(base, 2); } in cbo_flush()
85 return n != 0 && (n & (n - 1)) == 0; in is_power_of_2()
140 if (i % 2) in test_zicboz()
145 char expected = i % 2 ? 0x0 : 0xa5; in test_zicboz()
185 "presence (present or not) is consistent for each hart\n", in check_no_zicbo_cpus()
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