Lines Matching +full:hart +full:- +full:2

1 .. SPDX-License-Identifier: GPL-2.0
4 Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux
9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
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21 enable or disable the redirection. In the case of RISC-V, 2 instructions,
23 to patch 2 instructions and expect that a concurrent read-side executes them
25 RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
29 preemption, we partially initialize each patchable function entry at boot-time,
36 is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
37 of immediate encoding space in RISC-V. To address the issue, we introduce
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47 migrate a task onto a new hart. If migration occurs after the userspace
49 new hart will no longer be clean. This is due to the behavior of fence.i only
50 affecting the hart that it is called on. Thus, the hart that the task has been
55 userspace. The syscall performs a one-off icache flushing operation. The prctl
61 when the memory map being used by a hart changes. If the prctl() context caused
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73 .. kernel-doc:: arch/riscv/mm/cacheflush.c