| /linux/Documentation/hwmon/ |
| H A D | via686a.rst | 6 * Via VT82C686A, VT82C686B Southbridge Integrated Hardware Monitor
10 Addresses scanned: ISA in PCI-space encoded address
12 Datasheet: On request through web form (http://www.via.com.tw/en/resources/download-center/)
15 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
16 - Mark D. Studebaker <mdsxyz123@yahoo.com>
17 - Bob Dougherty <bobd@stanford.edu>
18 - (Some conversion-factor data were contributed by
19 - Jonathan Teh Soon Yew <j.teh@iname.com>
20 - and Alex van Kaam <darkside@chello.nl>.)
23 -----------------
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|
| H A D | sis5595.rst | 6 * Silicon Integrated Systems Corp. SiS5595 Southbridge Hardware Monitor
10 Addresses scanned: ISA in PCI-space encoded address
18 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
19 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
20 - Aurelien Jarno <aurelien@aurel32.net> 2.6 port
22 SiS southbridge has a LM78-like chip integrated on the same IC.
55 -----------------
69 -----------
71 The SiS5595 southbridge has integrated hardware monitor functions. It also
72 has an I2C bus, but this driver only supports the hardware monitor. For the
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| H A D | lm78.rst | 6 * National Semiconductor LM78 / LM78-J
10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 - Frodo Looijaard <frodol@dds.nl>
29 - Jean Delvare <jdelvare@suse.de>
32 -----------
34 This driver implements support for the National Semiconductor LM78, LM78-J
35 and LM79. They are described as 'Microprocessor System Hardware Monitors'.
38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
45 Temperatures are measured in degrees Celsius. An alarm is triggered once
[all …]
|
| H A D | lm87.rst | 10 Addresses scanned: I2C 0x2c - 0x2e
18 Addresses scanned: I2C 0x2c - 0x2e
24 - Frodo Looijaard <frodol@dds.nl>,
25 - Philip Edelbrock <phil@netroedge.com>,
26 - Mark Studebaker <mdsxyz123@yahoo.com>,
27 - Stephen Rousset <stephen.rousset@rocketlogix.com>,
28 - Dan Eaton <dan.eaton@rocketlogix.com>,
29 - Jean Delvare <jdelvare@suse.de>,
30 - Original 2.6 port Jeff Oliver
33 -----------
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| H A D | gl518sm.rst | 21 - Frodo Looijaard <frodol@dds.nl>,
22 - Kyösti Mälkki <kmalkki@cc.hut.fi>
23 - Hong-Gunn Chew <hglinux@gunnet.org>
24 - Jean Delvare <jdelvare@suse.de>
27 -----------
46 situation. Measurements are guaranteed between -10 degrees and +110
47 degrees, with a accuracy of +/-3 degrees.
50 triggered if the rotation speed has dropped below a programmable limit. In
51 case when you have selected to turn fan1 off, no fan1 alarm is triggered.
59 An alarm is triggered if the voltage has crossed a programmable minimum or
[all …]
|
| H A D | lm80.rst | 10 Addresses scanned: I2C 0x28 - 0x2f
20 Addresses scanned: I2C 0x28 - 0x2f
28 - Frodo Looijaard <frodol@dds.nl>,
29 - Philip Edelbrock <phil@netroedge.com>
32 -----------
35 It is described as a 'Serial Interface ACPI-Compatible Microprocessor
36 System Hardware Monitor'. The LM96080 is a more recent incarnation,
48 is unclear about this). Measurements are guaranteed between -55 and
53 triggered if the rotation speed has dropped below a programmable limit. Fan
60 An alarm is triggered if the voltage has crossed a programmable minimum
[all …]
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| H A D | smsc47m1.rst | 44 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
45 - With assistance from Bruce Allen <ballen@uwm.edu>, and his
48 - http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
50 - Gabriele Gorla <gorlik@yahoo.com>,
51 - Jean Delvare <jdelvare@suse.de>
54 -----------
59 The LPC47M15x, LPC47M192 and LPC47M292 chips contain a full 'hardware
61 hardware monitoring block is not supported by this driver, use the
68 triggered if the rotation speed has dropped below a programmable limit. Fan
76 If an alarm triggers, it will remain triggered until the hardware register
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|
| H A D | w83791d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
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| H A D | it87.rst | 174 - Christophe Gauthron
175 - Jean Delvare <jdelvare@suse.de>
179 -----------------
192 misconfigured by BIOS - PWM values would be inverted. This option tries
209 Provided since there are reports that system-wide acpi_enfore_resources=lax
216 Hardware Interfaces
217 -------------------
219 All the chips supported by this driver are LPC Super-I/O chips, accessed
220 through the LPC bus (ISA-like I/O ports). The IT8712F additionally has an
221 SMBus interface to the hardware monitoring functions. This driver no
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| H A D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
49 hardware monitoring chipsets, not only controlling and monitoring three fans,
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
[all …]
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
17 framework for its hardware implementation is alike to SPI bus and its timing
21 48 hardware channels to access analog chip. For 2 software read/write channels,
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| /linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,rpmh-rsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
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| /linux/Documentation/devicetree/bindings/thermal/ |
| H A D | nvidia,tegra124-soctherm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
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| /linux/drivers/iio/buffer/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 tristate "IIO callback buffer used for push in-kernel interfaces"
10 Should be selected by any drivers that do in-kernel push
37 to another device in hardware. In this case buffers for data transfers
38 are handled by hardware.
51 tristate "Industrial I/O triggered buffer support"
55 Provides helper functions for setting up triggered buffers.
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-dqevent.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DQEVENT - Dequeue event
45 .. flat-table:: struct v4l2_event
46 :header-rows: 0
47 :stub-columns: 0
50 * - __u32
51 - ``type``
52 - Type of the event, see :ref:`event-type`.
53 * - union {
54 - ``u``
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| H A D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
17 .. _flash-controls-use-cases:
24 ------------------------------------------
34 Synchronised LED flash (hardware strobe)
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
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| /linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | qcom,bcm-voter.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm BCM-Voter Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
13 The Bus Clock Manager (BCM) is a dedicated hardware accelerator that manages
22 - qcom,bcm-voter
24 qcom,tcs-wait:
26 Optional mask of which TCSs (Triggered Command Sets) wait for completion
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| /linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | mediatek,mt6370-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/mediatek,mt6370-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
18 const: mediatek,mt6370-charger
25 After the hardware of MT6370 completes the BC1.2 detection,
26 IRQ "MT6370_IRQ_ATTACH" will be triggered, and the driver will know
28 When the IRQ "MT6370_IRQ_CHG_MIVR" is triggered, it means that the
29 hardware enters the "Minimum Input Voltage Regulation loop" and
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| /linux/Documentation/core-api/ |
| H A D | memory-allocation.rst | 35 :ref:`Documentation/core-api/mm-api.rst <mm-api-gfp-flags>` provides
43 direct reclaim may be triggered under memory pressure; the calling
53 * Untrusted allocations triggered from userspace should be a subject
67 example may be a hardware allocation that maps data directly into
79 :ref:`Documentation/core-api/gfp_mask-from-fs-io.rst <gfp_mask_from_fs_io>`.
82 used to ensure that the allocated memory is accessible by hardware
85 And even with hardware with restrictions it is preferable to use
89 ------------------------------
94 * ``GFP_KERNEL & ~__GFP_RECLAIM`` - optimistic allocation without _any_
100 * ``GFP_KERNEL & ~__GFP_DIRECT_RECLAIM`` (or ``GFP_NOWAIT``)- optimistic
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| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
19 to Linux developers working with embedded and custom hardware. Each GPIO
21 (BGA) packages. Board schematics show which external hardware connects to
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
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| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
18 hardware interrupts for SIC1 and SIC2
[all …]
|
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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|
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_hw_fence_types.h | 1 /* SPDX-License-Identifier: MIT */
9 #include <linux/dma-fence.h>
10 #include <linux/iosys-map.h>
19 * struct xe_hw_fence_irq - hardware fence IRQ handler
21 * One per engine class, signals completed xe_hw_fences, triggered via hw engine
38 * struct xe_hw_fence_ctx - hardware fence context
40 * The context for a hardware fence. 1 to 1 relationship with xe_engine. Points
44 /** @gt: graphics tile of hardware fence context */
48 /** @dma_fence_ctx: dma fence context for hardware fence */
50 /** @next_seqno: next seqno for hardware fence */
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| /linux/drivers/leds/blink/ |
| H A D | Kconfig | 10 BCM63138 SoC. The same hardware block is known to be also used
13 If compiled as module it will be called leds-bcm63138.
22 gateway-on-a-chip SoC to be shipped on mid and high end home
26 The driver supports hardware blinking and the LEDs can be configured
27 to be triggered by software/CPU or by hardware.
31 will be called leds-lgm-sso.
|