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/linux/arch/s390/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "Accelerated Cryptographic Algorithms for CPU (s390)"
6 tristate "Hash functions: SHA3-224 and SHA3-256"
9 SHA3-224 and SHA3-256 secure hash algorithms (FIPS 202)
16 tristate "Hash functions: SHA3-384 and SHA3-512"
19 SHA3-384 and SHA3-512 secure hash algorithms (FIPS 202)
29 GCM GHASH hash function (NIST SP800-38D)
42 Length-preserving ciphers: AES with ECB, CBC, XTS, and CTR modes
46 As of z9 the ECB and CBC modes are hardware accelerated
49 As of z10 the ECB and CBC modes are hardware accelerated
[all …]
/linux/drivers/video/fbdev/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 (accelerated) version.
42 This is used by drivers that don't provide their own (accelerated)
51 (accelerated) version.
57 Allow I/O memory frame-buffer functions to work on displays with 1, 2
67 (accelerated) version and the framebuffer is in system RAM.
74 This is used by drivers that don't provide their own (accelerated)
83 (accelerated) version and the framebuffer is in system RAM.
89 Allow virtual memory frame-buffer functions to work on displays with 1, 2
97 Allow generic frame-buffer to provide get_fb_unmapped_area
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/linux/Documentation/networking/
H A Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
[all …]
/linux/Documentation/fb/
H A Dmatroxfb.rst2 matroxfb - Framebuffer driver for Matrox devices
13 * Most important: boot logo :-)
31 box) and matroxfb (for graphics mode). You should not compile-in vesafb
32 unless you have primary display on non-Matrox VBE2.0 device (see
40 -------------
55 -------------------------
70 ----------
83 Non-listed number can be achieved by more complicated command-line, for
90 XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
94 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
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/linux/include/linux/
H A Dif_vlan.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 * According to 802.3ac, the packet can be 4 bytes longer. --Klika Jan
31 * struct vlan_hdr - vlan header
41 * struct vlan_ethhdr - vlan ethernet header (ethhdr + vlan_hdr)
70 return (struct vlan_ethhdr *)skb->data; in skb_vlan_eth_hdr()
82 #define skb_vlan_tag_present(__skb) (!!(__skb)->vlan_all)
83 #define skb_vlan_tag_get(__skb) ((__skb)->vlan_tci)
84 #define skb_vlan_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK)
85 #define skb_vlan_tag_get_cfi(__skb) (!!((__skb)->vlan_tci & VLAN_CFI_MASK))
86 #define skb_vlan_tag_get_prio(__skb) (((__skb)->vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT)
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/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
H A Dkconfig.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
45 | Requires CONFIG_MLX5_CORE_EN to provide an accelerated interface for the rdma
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
72 | Build support for MACsec cryptography-offload acceleration in the NIC.
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/linux/arch/powerpc/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "Accelerated Cryptographic Algorithms for CPU (powerpc)"
10 Block ciphers: AES cipher algorithms (FIPS-197)
11 Length-preserving ciphers: AES with ECB, CBC, CTR, and XTS modes
14 - SPE (Signal Processing Engine) extensions
17 - Processor Type: Freescale 8500
18 - CPU selection: e500 (8540)
21 without hardware AES acceleration (e.g. caam crypto). It reduces the
25 tables or 256 bytes S-boxes.
36 AEAD cipher: AES cipher algorithms (FIPS-197)
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/linux/Documentation/devicetree/bindings/crypto/
H A Dintel,keembay-ocs-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
14 hardware-accelerated AES/SM4 encryption/decryption.
18 const: intel,keembay-ocs-aes
30 - compatible
31 - reg
32 - interrupts
[all …]
H A Dintel,keembay-ocs-hcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Declan Murphy <declan.murphy@intel.com>
11 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
15 provides hardware-accelerated hashing and HMAC.
19 const: intel,keembay-ocs-hcu
31 - compatible
32 - reg
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/linux/Documentation/devicetree/bindings/leds/
H A Dleds-spi-byte.txt4 - one LED is controlled by a single byte on MOSI
5 - the value of the byte gives the brightness between two values (lowest to
7 - no return value is necessary (no MISO signal)
12 Depending on the compatible string some special functions (like hardware
13 accelerated blinking) might can be supported too.
16 configured in a sub-node in the device node.
19 - compatible: should be one of
20 * "ubnt,acb-spi-led" microcontroller (SONiX 8F26E611LA) based device
23 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
26 LED sub-node properties:
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/linux/drivers/net/ethernet/sfc/siena/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 This driver supports 10-gigabit Ethernet cards based on
13 will be called sfc-siena.
15 bool "Solarflare SFC9000-family MTD support"
19 This exposes the on-board flash and/or EEPROM as MTD devices
23 bool "Solarflare SFC9000-family hwmon support"
27 This exposes the on-board firmware-managed sensors as a
28 hardware monitor device.
30 bool "Solarflare SFC9000-family SR-IOV support"
35 features, allowing accelerated network performance in
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H A Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
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/linux/arch/x86/kernel/apic/
H A Dx2apic_savic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure AVIC Support (SEV-SNP Guests)
12 #include <linux/percpu-defs.h>
33 return &per_cpu_ptr(savic_page, cpu)->regs[offset]; in get_reg_bitmap()
51 * result in #VC exception (for non-accelerated register accesses)
113 IS_ALIGNED(reg - 4, 16)), in savic_read()
126 * On WRMSR to APIC_SELF_IPI register by the guest, Secure AVIC hardware
128 * hardware evaluates the new APIC_IRR update for interrupt injection to
129 * the vCPU. So, self IPIs are hardware-accelerated.
234 if (IS_ALIGNED(reg - 4, 16)) { in savic_write()
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/linux/lib/xz/
H A Dxz_crc32.c1 // SPDX-License-Identifier: 0BSD
4 * CRC32 using the polynomial from IEEE-802.3
7 * Igor Pavlov <https://7-zip.org/>
12 * The fastest versions of xz_crc32() on modern CPUs without hardware
13 * accelerated CRC instruction are 3-5 times as fast as this version,
20 * STATIC_RW_DATA is used in the pre-boot environment on some architectures.
40 r = (r >> 1) ^ (poly & ~((r & 1) - 1)); in xz_crc32_init()
54 --size; in xz_crc32()
/linux/lib/crc/s390/
H A Dcrc32.h1 // SPDX-License-Identifier: GPL-2.0
3 * CRC-32 implemented with the z/Architecture Vector Extension Facility.
11 #include "crc32-vx.h"
15 #define VX_ALIGN_MASK (VX_ALIGNMENT - 1)
18 * DEFINE_CRC32_VX() - Define a CRC-32 function using the vector extension
20 * Creates a function to perform a particular CRC-32 computation. Depending
21 * on the message buffer, the hardware-accelerated or software implementation
35 prealign = VX_ALIGNMENT - \
37 datalen -= prealign; \
/linux/Documentation/userspace-api/
H A Diommufd.rst1 .. SPDX-License-Identifier: GPL-2.0+
20 I/O page tables for all IOMMUs, with room in the design to add non-generic
21 features to cater to specific hardware functionality.
31 --------------------
35 - IOMMUFD_OBJ_IOAS, representing an I/O address space (IOAS), allowing map/unmap
41 - IOMMUFD_OBJ_DEVICE, representing a device that is bound to iommufd by an
44 - IOMMUFD_OBJ_HWPT_PAGING, representing an actual hardware I/O page table
48 feature flag. This can be either an UNMANAGED stage-1 domain for a device
49 running in the user space, or a nesting parent stage-2 domain for mappings
50 from guest-level physical addresses to host-level physical addresses.
[all …]
/linux/drivers/net/ethernet/sfc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "Solarflare SFC9100/EF100-family support"
27 This driver supports 10/40-gigabit Ethernet cards based on
28 the Solarflare SFC9100-family controllers.
30 It also supports 10/25/40/100-gigabit Ethernet cards based
36 bool "Solarflare SFC9100-family MTD support"
40 This exposes the on-board flash and/or EEPROM as MTD devices
45 bool "Solarflare SFC9100-family hwmon support"
49 This exposes the on-board firmware-managed sensors as a
50 hardware monitor device.
[all …]
H A Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
126 * struct efx_tx_buffer - buffer state for a TX descriptor
[all …]
/linux/Documentation/scsi/
H A Dcxgb3i.rst1 .. SPDX-License-Identifier: GPL-2.0
12 (DDP) where the hardware handles the expensive byte touching operations, such
16 - iSCSI PDU digest generation and verification
23 - Direct Data Placement (DDP)
25 S3 h/w can directly place the iSCSI Data-In or Data-Out PDU's
26 payload into pre-posted final destination host-memory buffers based
27 on the Initiator Task Tag (ITT) in Data-In or Target Task Tag (TTT)
28 in Data-Out PDUs.
30 - PDU Transmit and Recovery
41 if possible, will be directly placed into the pre-posted host DDP
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
34 What: /sys/bus/platform/devices/dfl-port.0/ap2_event
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/linux/fs/btrfs/
H A Dzlib.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright © 2001-2007 Red Hat, Inc.
26 /* workspace buffer size for s390 zlib hardware support */
42 workspace->level = level; in zlib_get_workspace()
51 kvfree(workspace->strm.workspace); in zlib_free_workspace()
52 kfree(workspace->buf); in zlib_free_workspace()
57 * For s390 hardware acceleration, the buffer size should be at least
60 * But if bs > ps we can have large enough folios that meet the s390 hardware
74 const u32 blocksize = fs_info->sectorsize; in zlib_alloc_workspace()
80 return ERR_PTR(-ENOMEM); in zlib_alloc_workspace()
[all …]
/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
[all …]
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-mac.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
11 * Macintosh-specific tags (all __be32)
29 * Macintosh hardware profile data - unused, see macintosh.h for
48 #define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
105 #define MAC_MODEL_Q605_ACC 95 /* Q605 accelerated to 33 MHz */
/linux/drivers/iommu/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 bool "Support the legacy \"mmu-masters\" devicetree bindings"
22 Support for the badly designed and deprecated "mmu-masters"
36 securely, and you don't want to boot with the 'arm-smmu.disable_bypass=0'
40 Note that 'arm-smmu.disable_bypass=1' will still take precedence.
47 MMU-500's next-page prefetcher for sake of 4 known errata.
51 Refer silicon-errata.rst for info on errata IDs.
66 hardware found in QTI platforms. This include support for
108 with accelerated virtual IOMMUs.
113 tristate "KUnit tests for arm-smmu-v3 driver" if !KUNIT_ALL_TESTS
[all …]
/linux/drivers/char/agp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 AGP (Accelerated Graphics Port) is a bus system mainly used to
20 write-combining with MTRR support on the AGP bus. Without it, OpenGL
37 For the ALi-chipset question, ALi suggests you refer to
43 This is a hardware limitation. AGP 1x seems to be fine, though.
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
64 X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
117 AGP bus adapter on HP PA-RISC machines (Ok, just on the C8000

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