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/linux/drivers/clk/spear/
H A Dclk-gpt-synth.c9 #define pr_fmt(fmt) "clk-gpt-synth: " fmt
24 * Calculates gpt synth clk rate for different values of mscale and nscale
34 struct clk_gpt *gpt = to_clk_gpt(hw); in gpt_calc_rate() local
35 struct gpt_rate_tbl *rtbl = gpt->rtbl; in gpt_calc_rate()
45 struct clk_gpt *gpt = to_clk_gpt(hw); in clk_gpt_determine_rate() local
49 gpt_calc_rate, gpt->rtbl_cnt, &unused); in clk_gpt_determine_rate()
57 struct clk_gpt *gpt = to_clk_gpt(hw); in clk_gpt_recalc_rate() local
61 if (gpt->lock) in clk_gpt_recalc_rate()
62 spin_lock_irqsave(gpt->lock, flags); in clk_gpt_recalc_rate()
64 val = readl_relaxed(gpt->reg); in clk_gpt_recalc_rate()
[all …]
H A DMakefile6 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
H A Dclk.h68 /* GPT clk */
/linux/drivers/clocksource/
H A Dtimer-imx-gpt.c73 const struct imx_gpt_data *gpt; member
155 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; in mxc_clocksource_init()
206 /* Disable interrupt in GPT module */ in mxc_shutdown()
207 imxtm->gpt->gpt_irq_disable(imxtm); in mxc_shutdown()
209 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_shutdown()
211 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); in mxc_shutdown()
214 imxtm->gpt->gpt_irq_acknowledge(imxtm); in mxc_shutdown()
227 /* Disable interrupt in GPT module */ in mxc_set_oneshot()
228 imxtm->gpt->gpt_irq_disable(imxtm); in mxc_set_oneshot()
231 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_set_oneshot()
[all …]
H A Dtimer-pistachio.c112 /* Disable GPT local before loading reload value */ in pistachio_clksrc_enable()
120 /* Disable GPT local */ in pistachio_clksrc_disable()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-poeg.yaml7 title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
13 The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
14 disabled by using the port output enabling function for the GPT (POEG).
17 * Output-disable request from the GPT.
21 are controlled by the GPT module.
46 renesas,gpt:
48 description: phandle to gpt instance that serves the pwm operation.
68 - renesas,gpt
85 renesas,gpt = <&gpt>;
H A Dlantiq,pinctrl-xway.txt51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
/linux/arch/powerpc/boot/dts/
H A Dmpc5200b.dtsi64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
H A Dlite5200.dts63 compatible = "fsl,mpc5200-gpt";
70 compatible = "fsl,mpc5200-gpt";
76 compatible = "fsl,mpc5200-gpt";
82 compatible = "fsl,mpc5200-gpt";
88 compatible = "fsl,mpc5200-gpt";
94 compatible = "fsl,mpc5200-gpt";
100 compatible = "fsl,mpc5200-gpt";
106 compatible = "fsl,mpc5200-gpt";
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt84 timer@<addr> fsl,mpc5200-gpt General purpose timers
102 fsl,mpc5200-gpt nodes
107 the watchdog. The timer will function as a GPT if the timer api is used, and
109 mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110 gpt api call to this timer will fail with -EBUSY.
114 GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
117 - just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
123 An mpc5200-gpt can be used as a single line GPIO controller. To do so,
124 add the following properties to the gpt node:
131 An mpc5200-gpt can be used as a single line edge sensitive interrupt
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Drenesas,rzg2l-gpt.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
7 title: Renesas RZ/G2L General PWM Timer (GPT)
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
63 - renesas,r9a07g044-gpt # RZ/G2{L,LC}
64 - renesas,r9a07g054-gpt # RZ/V2L
65 - const: renesas,rzg2l-gpt
267 gpt: pwm@10048000 {
268 compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
/linux/drivers/pinctrl/
H A Dpinctrl-xway.c119 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
120 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
140 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
195 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
196 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
197 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
232 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
249 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
264 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
271 MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050.dtsi152 gpt: timer@401ec000 { label
153 compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
H A Dimx50.dtsi277 gpt: timer@53fa0000 { label
278 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
/linux/arch/powerpc/platforms/52xx/
H A DKconfig20 gpt nodes, then it is safe to use such gpt to reset the board,
H A Dmpc5200_simple.c16 * gpt nodes, then it is safe to use such gpt to reset the board,
H A Dmpc52xx_common.c110 { .compatible = "fsl,mpc5200-gpt", },
111 { .compatible = "mpc5200-gpt", }, /* old */
/linux/arch/arm/mach-spear/
H A Dspear3xx.c81 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear3xx_timer_init()
88 pr_err("%s:couldn't get %s as parent for gpt\n", in spear3xx_timer_init()
H A Dtime.c27 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
229 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear_setup_of_timer()
235 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); in spear_setup_of_timer()
H A Dspear13xx.c108 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear13xx_timer_init()
115 pr_err("%s:couldn't get %s as parent for gpt\n", __func__, in spear13xx_timer_init()
H A Dspear6xx.c378 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear6xx_timer_init()
385 pr_err("%s:couldn't get %s as parent for gpt\n", in spear6xx_timer_init()
/linux/arch/powerpc/include/asm/
H A Dmpc52xx.h106 /* GPT */
283 extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
285 extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
286 extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044l2-smarc.dts31 * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
H A Dr9a07g054l2-smarc.dts30 * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
/linux/include/linux/
H A Dmc6821.h14 * Richard Hirst, srh@gpt.co.uk)

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