/linux/Documentation/devicetree/bindings/gpio/ |
H A D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx AXI GPIO controller 10 - Neeli Srinivas <srinivas.neeli@amd.com> 13 The AXI GPIO design provides a general purpose input/output interface 14 to an AXI4-Lite interface. The AXI GPIO can be configured as either 15 a single or a dual-channel device. The width of each channel is 22 - xlnx,xps-gpio-1.00.a [all …]
|
/linux/Documentation/devicetree/bindings/auxdisplay/ |
H A D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert@linux-m68k.org> 15 interface, which can be used in either 4-bit or 8-bit mode. By using a 16 GPIO expander it is possible to use the driver with one of the popular I2C 24 data-gpios: 26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or 27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface. 29 - maxItems: 4 [all …]
|
/linux/drivers/gpio/ |
H A D | gpio-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Xilinx gpio driver for xps/axi_gpio IP. 5 * Copyright 2008 - 2013 Xilinx, Inc. 12 #include <linux/gpio/driver.h> 35 /* Read/Write access to the GPIO registers */ 45 * struct xgpio_instance - Stores information about GPIO device 46 * @gc: GPIO chip 48 * @hw_map: GPIO pin mapping on hardware side 49 * @sw_map: GPIO pin mapping on software side 50 * @state: GPIO write state shadow register [all …]
|
/linux/drivers/pinctrl/actions/ |
H A D | pinctrl-owl.h | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * Author: David Liu <liuwei@actions-semi.com> 18 #define MUX_PG(group_name, reg, shift, width) \ argument 27 .mfpctl_width = width, \ 28 .drv_reg = -1, \ 29 .drv_shift = -1, \ 30 .drv_width = -1, \ 31 .sr_reg = -1, \ 32 .sr_shift = -1, \ 33 .sr_width = -1, \ [all …]
|
H A D | pinctrl-owl.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * Author: David Liu <liuwei@actions-semi.com> 14 #include <linux/gpio/driver.h> 25 #include <linux/pinctrl/pinconf-generic.h> 31 #include "../pinctrl-utils.h" 32 #include "pinctrl-owl.h" 35 * struct owl_pinctrl - pinctrl state of the device 38 * @chip: gpio chip 70 u32 bit, u32 width) in owl_read_field() argument 74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field() [all …]
|
/linux/arch/arm/mach-s3c/ |
H A D | setup-sdhci-gpio-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0 7 // S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) 14 #include <linux/gpio.h> 16 #include "gpio-cfg.h" 18 #include "gpio-samsung.h" 20 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c64xx_setup_sdhci0_cfg_gpio() argument 22 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; in s3c64xx_setup_sdhci0_cfg_gpio() 24 /* Set all the necessary GPG pins to special-function 2 */ in s3c64xx_setup_sdhci0_cfg_gpio() 25 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); in s3c64xx_setup_sdhci0_cfg_gpio() 27 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { in s3c64xx_setup_sdhci0_cfg_gpio() [all …]
|
/linux/Documentation/devicetree/bindings/mtd/ |
H A D | gpio-control-nand.txt | 1 GPIO assisted NAND flash 3 The GPIO assisted NAND flash uses a memory mapped interface to 4 read/write the NAND commands and data and GPIO pins for the control 8 - compatible : "gpio-control-nand" 9 - reg : should specify localbus chip select and size used for the chip. The 12 - #address-cells, #size-cells : Must be present if the device has sub-nodes 14 - gpios : Specifies the GPIO pins to control the NAND device. The order of 15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional. 18 - bank-width : Width (in bytes) of the device. If not present, the width 20 - chip-delay : chip dependent delay for transferring data from array to [all …]
|
H A D | ti,gpmc-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tony Lindgren <tony@atomide.com> 11 - Roger Quadros <rogerq@kernel.org> 20 - enum: 21 - ti,am64-nand 22 - ti,omap2-nand 29 - description: Interrupt for fifoevent [all …]
|
H A D | mtd-physmap.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 10 - Rob Herring <robh@kernel.org> 17 - $ref: mtd.yaml# 18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 23 - items: 24 - enum: [all …]
|
/linux/tools/testing/selftests/gpio/ |
H A D | gpio-mockup.sh | 1 #!/bin/bash -efu 2 # SPDX-License-Identifier: GPL-2.0 7 #4: skip test - including run as non-root user 13 module="gpio-mockup" 29 echo "$0 [-frv] [-t type]" 30 echo "-f: full test (minimal set run by default)" 31 echo "-r: test random lines as well as fence posts" 32 echo "-t: interface type:" 33 echo " cdev (character device ABI) - default" 36 echo "-v: verbose progress reporting" [all …]
|
/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mn-rve-gateway.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/usb/pd.h> 9 #include "imx8mn-var-som.dtsi" 13 compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; 15 crystal_duart_24m: crystal-duart-24m { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 clock-frequency = <24000000>; 21 gpio-keys { [all …]
|
H A D | fsl-ls1028a-kontron-sl28.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Device Tree file for the Kontron SMARC-sAL28 board. 9 /dts-v1/; 10 #include "fsl-ls1028a.dtsi" 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/input/input.h> 16 model = "Kontron SMARC-sAL28"; 33 compatible = "gpio-keys"; 35 power-button { [all …]
|
/linux/arch/riscv/boot/dts/sophgo/ |
H A D | cv18xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 #include <dt-bindings/clock/sophgo,cv1800.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <25000000>; 24 d-cache-block-size = <64>; [all …]
|
/linux/arch/arm/boot/dts/marvell/ |
H A D | orion5x-rd88f5182-nas.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 4 /dts-v1/; 6 #include <dt-bindings/gpio/gpio.h> 7 #include "orion5x-mv88f5182.dtsi" 11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; 20 stdout-path = &uart0; 30 gpio-leds { 31 compatible = "gpio-leds"; 32 pinctrl-0 = <&pmx_debug_led>; [all …]
|
/linux/arch/arm64/boot/dts/bitmain/ |
H A D | bm1880.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/clock/bm1880-clock.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/reset/bitmain,bm1880-reset.h> 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 18 #address-cells = <1>; 19 #size-cells = <0>; 23 compatible = "arm,cortex-a53"; [all …]
|
/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tony Lindgren <tony@atomide.com> 21 - enum: 22 - pinctrl-single 23 - pinconf-single 24 - items: 25 - enum: [all …]
|
/linux/arch/arc/boot/dts/ |
H A D | axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 14 compatible = "simple-bus"; 15 #address-cells = <1>; 16 #size-cells = <1>; 18 interrupt-parent = <&mb_intc>; 20 creg_rst: reset-controller@11220 { 21 compatible = "snps,axs10x-reset"; 22 #reset-cells = <1>; 27 compatible = "snps,axs10x-i2s-pll-clock"; [all …]
|
/linux/arch/arm64/boot/dts/marvell/ |
H A D | ac5-98dx25xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <2>; 21 #size-cells = <0>; 23 cpu-map { 36 compatible = "arm,cortex-a55"; [all …]
|
H A D | armada-3720-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (DB-88F3720-DDR3) 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 14 /dts-v1/; 16 #include <dt-bindings/gpio/gpio.h> 17 #include "armada-372x.dtsi" 20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; 21 compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3700"; 24 stdout-path = "serial0:115200n8"; 32 exp_usb3_vbus: usb3-vbus { [all …]
|
/linux/arch/arm/boot/dts/microchip/ |
H A D | sama5d3xmb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; 21 bus-width = <4>; 22 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; 31 spi-max-frequency = <50000000>; 37 atmel,clk-from-rk-pin; 50 clock-names = "mclk"; 58 pinctrl-names = "default"; [all …]
|
/linux/drivers/auxdisplay/ |
H A D | hd44780.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu> 6 * Copyright (C) 2016-2017 Glider bvba 10 #include <linux/gpio/consumer.h> 21 /* Order does matter due to writing to GPIO array subsets! */ 43 struct hd44780_common *hdc = lcd->drvdata; in hd44780_backlight() 44 struct hd44780 *hd = hdc->hd44780; in hd44780_backlight() 46 if (hd->pins[PIN_CTRL_BL]) in hd44780_backlight() 47 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_BL], on); in hd44780_backlight() 55 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_E], 1); in hd44780_strobe_gpio() [all …]
|
/linux/arch/mips/boot/dts/ingenic/ |
H A D | cu1000-neo.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/clock/ingenic,sysost.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 10 compatible = "yna,cu1000-neo", "ingenic,x1000e"; 11 model = "YSH & ATIL General Board CU1000-Neo"; 18 stdout-path = "serial2:115200n8"; 27 compatible = "gpio-leds"; 28 led-0 { [all …]
|
H A D | cu1830-neo.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/clock/ingenic,sysost.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 10 compatible = "yna,cu1830-neo", "ingenic,x1830"; 11 model = "YSH & ATIL General Board CU1830-Neo"; 18 stdout-path = "serial1:115200n8"; 27 compatible = "gpio-leds"; 28 led-0 { [all …]
|
/linux/arch/powerpc/boot/dts/ |
H A D | pcm032.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source 5 * Copyright (C) 2006-2009 Pengutronix 11 &gpt0 { fsl,has-wdt; }; 12 &gpt2 { gpio-controller; }; 13 &gpt3 { gpio-controller; }; 14 &gpt4 { gpio-controller; }; 15 &gpt5 { gpio-controller; }; 16 &gpt6 { gpio-controller; }; 17 &gpt7 { gpio-controller; }; [all …]
|
/linux/drivers/staging/fbtft/ |
H A D | fb_tls8204.c | 1 // SPDX-License-Identifier: GPL-2.0+ 15 #include <linux/gpio/consumer.h> 22 #define WIDTH 84 macro 24 #define TXBUFLEN WIDTH 31 MODULE_PARM_DESC(bs, "BS[2:0] Bias voltage level: 0-7 (default: 4)"); 35 par->fbtftops.reset(par); in init_display() 39 * 2:0 PD - Powerdown control: chip is active in init_display() 40 * 1:0 V - Entry mode: horizontal addressing in init_display() 41 * 0:1 H - Extended instruction set control: in init_display() 49 * 2:x BS2 - Bias System in init_display() [all …]
|