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/linux/drivers/gpio/
H A Dgpio-en7523.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/gpio/driver.h>
7 #include <linux/gpio/generic.h>
15 * struct airoha_gpio_ctrl - Airoha GPIO driver data
29 static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, in airoha_dir_set() argument
32 struct airoha_gpio_ctrl *ctrl = gpiochip_get_data(gc); in airoha_dir_set() local
33 u32 dir = ioread32(ctrl->dir[gpio / 16]); in airoha_dir_set()
34 u32 output = ioread32(ctrl->output); in airoha_dir_set()
35 u32 mask = BIT((gpio % 16) * 2); in airoha_dir_set()
39 output |= BIT(gpio); in airoha_dir_set()
[all …]
H A Dgpio-idt3243x.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/gpio/driver.h>
6 #include <linux/gpio/generic.h>
23 void __iomem *gpio; member
30 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_dispatch() local
37 pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND); in idt_gpio_dispatch()
38 pending &= ~ctrl->mask_cache; in idt_gpio_dispatch()
39 for_each_set_bit(bit, &pending, gc->ngpio) { in idt_gpio_dispatch()
40 virq = irq_find_mapping(gc->irq.domain, bit); in idt_gpio_dispatch()
51 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_irq_set_type() local
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H A Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/gpio/driver.h>
5 #include <linux/gpio/generic.h>
29 /* Two bits per GPIO in IMR registers */
42 * struct realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
46 * @cpumask_base: Base address of the per-CPU interrupt mask registers
47 * @cpu_irq_maskable: CPUs that can receive GPIO interrupts
51 * @bank_read: Read a bank setting as a single 32-bit value
52 * @bank_write: Write a bank setting as a single 32-bit value
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H A Dgpio-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atheros AR71XX/AR724X/AR913X GPIO API support
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
12 #include <linux/gpio/driver.h>
13 #include <linux/gpio/generic.h>
14 #include <linux/gpio/machine.h> /* For WLAN GPIOs */
45 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) in ath79_gpio_read() argument
47 return readl(ctrl->base + reg); in ath79_gpio_read()
50 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, in ath79_gpio_write() argument
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H A Dgpio-max77759.c1 // SPDX-License-Identifier: GPL-2.0-only
6 // GPIO driver for Maxim MAX77759
11 #include <linux/gpio/driver.h>
64 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ; in max77759_gpio_maxq_gpio_trigger_read()
66 ret = max77759_maxq_command(chip->max77759, cmd, rsp); in max77759_gpio_maxq_gpio_trigger_read()
70 return rsp->rsp[1]; in max77759_gpio_maxq_gpio_trigger_read()
78 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE; in max77759_gpio_maxq_gpio_trigger_write()
79 cmd->cmd[1] = trigger; in max77759_gpio_maxq_gpio_trigger_write()
81 return max77759_maxq_command(chip->max77759, cmd, NULL); in max77759_gpio_maxq_gpio_trigger_write()
90 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ; in max77759_gpio_maxq_gpio_control_read()
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/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l45.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
31 '#sound-dai-cells':
34 reset-gpios:
37 vdd-a-supply:
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/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-iomega_ix2_200.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
8 model = "Iomega StorCenter ix2-200";
9 compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
33 pinctrl-names = "default";
35 pmx_button_reset: pmx-button-reset {
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H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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H A Darmada-370-synology-ds213j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
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/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admfm2000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kim Seer Paller <kimseer.paller@analog.com>
22 - adi,admfm2000
24 '#address-cells':
27 '#size-cells':
31 "^channel@[0-1]$":
44 adi,mixer-mode:
52 switch-gpios:
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/linux/Documentation/devicetree/bindings/iio/amplifiers/
H A Dadi,hmc425a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Digital Step Attenuator IIO devices with gpio interface.
15 ADRF5750 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz
16 https://www.analog.com/media/en/technical-documentation/data-sheets/adrf5740.pdf
18 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
19 https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
21 HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz
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/linux/Documentation/devicetree/bindings/leds/
H A Dkinetic,ktd2692.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
27 ctrl-gpios:
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H A Dleds-lt3593.txt4 - compatible: Should be "lltc,lt3593".
5 - lltc,ctrl-gpios: A handle to the GPIO that is connected to the 'CTRL'
9 configured in a sub-node in the device node.
11 Optional sub-node properties:
12 - function: See Documentation/devicetree/bindings/leds/common.txt
13 - color: See Documentation/devicetree/bindings/leds/common.txt
14 - label: A label for the LED. If none is given, the LED will be
16 - linux,default-trigger: The default trigger for the LED.
18 - default-state: The initial state of the LED.
26 #include <dt-bindings/leds/common.h>
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/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dkinetic,ktd2801.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Kinetic Technologies KTD2801 one-wire backlight
10 - Duje Mihanović <duje.mihanovic@skole.hr>
14 by a single GPIO line. The driver can be controlled with a PWM signal
15 or by pulsing the GPIO line to set the backlight level. This is called
19 - $ref: common.yaml#
25 ctrl-gpios:
28 default-brightness: true
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/linux/arch/m68k/include/asm/
H A Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
35 * @mpp_gpio_req: (optional) special function to request gpio
36 * @mpp_gpio_dir: (optional) special function to set gpio direction
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
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/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,ns2-drd-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Hauke Mehrtens <hauke@hauke-m.de>
12 - Rafał Miłecki <zajec5@gmail.com>
16 const: brcm,ns2-drd-phy
20 - description: DRD ICFG configurations
21 - description: DRD IDM reset
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
23 #include <linux/gpio/driver.h>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
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/linux/drivers/platform/surface/aggregator/
H A Dcontroller.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
11 #include <linux/gpio/consumer.h>
38 /* -- Safe counters. -------------------------------------------------------- */
41 * ssh_seq_reset() - Reset/initialize sequence ID counter.
46 WRITE_ONCE(c->value, 0); in ssh_seq_reset()
50 * ssh_seq_next() - Get next sequence ID.
57 u8 old = READ_ONCE(c->value); in ssh_seq_next()
61 while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { in ssh_seq_next()
70 * ssh_rqid_reset() - Reset/initialize request ID counter.
[all …]
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Provides access to a SAM-over-SSH connected EC via a controller device.
10 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
16 #include <linux/gpio/consumer.h>
37 /* -- Static controller reference. ------------------------------------------ */
47 * ssam_get_controller() - Get reference to SSAM controller.
57 struct ssam_controller *ctrl; in ssam_get_controller() local
61 ctrl = __ssam_controller; in ssam_get_controller()
62 if (!ctrl) in ssam_get_controller()
65 if (WARN_ON(!kref_get_unless_zero(&ctrl->kref))) in ssam_get_controller()
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/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/mdio-bitbang.h>
28 struct mdiobb_ctrl ctrl; member
35 /* FIXME: If any other users of GPIO crop up, then these will have to
38 * bind the ports to a GPIO driver, and have this be a client of it.
55 static inline void mdio_dir(struct mdiobb_ctrl *ctrl, int dir) in mdio_dir() argument
57 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); in mdio_dir()
60 bb_set(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
62 bb_clr(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
65 in_be32(bitbang->dir); in mdio_dir()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
22 const: fsl,imx93-mipi-dsi
26 - description: apb clock
27 - description: pixel clock
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/linux/drivers/pinctrl/qcom/
H A Dpinctrl-spmi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/gpio/driver.h>
20 #include <linux/pinctrl/pinconf-generic.h>
24 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
27 #include "../pinctrl-utils.h"
35 /* GPIO peripheral type and subtype out_values */
102 * Output type - indicates pin should be configured as push-pull,
142 * struct pmic_gpio_pad - keep current GPIO settings
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