/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Exynos5410 SoC pin-mux and pin-config device tree source 9 #include "exynos-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 16 interrupt-controller; 17 #interrupt-cells = <2>; 20 gpa1: gpa1-gpio-bank { 21 gpio-controller; [all …]
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H A D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpy7: gpy7-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpx0: gpx0-gpio-bank { [all …]
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H A D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 22 gpa0: gpa0-gpio-bank { 23 gpio-controller; 24 #gpio-cells = <2>; [all …]
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H A D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source 5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2011-2012 Linaro Ltd. 10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device 14 #include "exynos-pinctrl.h" 17 gpa0: gpa0-gpio-bank { 18 gpio-controller; 19 #gpio-cells = <2>; 21 interrupt-controller; [all …]
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H A D | exynos3250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ 23 pin- ## _pin { \ 25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ [all …]
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H A D | s5pv210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's S5PV210 SoC device tree source - pin control-related 6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. 11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are 15 #include "s5pv210-pinctrl.h" 18 pin- ## _pin { \ 20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \ 21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \ 25 gpa0: gpa0-gpio-bank { 26 gpio-controller; [all …]
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/linux/tools/testing/selftests/gpio/ |
H A D | gpio-sim.sh | 2 # SPDX-License-Identifier: GPL-2.0 6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim" 7 MODULE="gpio-sim" 11 echo "GPIO $MODULE test FAIL" 17 echo "GPIO $MODULE test SKIP" 25 BANK=`basename $FILE` 26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then 30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line` 33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then 34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \ [all …]
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/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2021 Tesla, Inc. 11 #include "fsd-pinctrl.h" 14 gpf0: gpf0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 18 interrupt-controller; 19 #interrupt-cells = <2>; [all …]
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the 4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0) 5 and multiple alternate functions(ALT1 - ALTx) that directly connect 8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and 12 gpio driver to configure a pin. 14 GPIO bank can have one of the two possible types of interrupt-wirings. 16 First type is via irqmux, single interrupt is used by multiple gpio banks. This 20 | |----> [gpio-bank (n) ] 21 | |----> [gpio-bank (n + 1)] 22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] [all …]
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H A D | samsung,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 - Tomasz Figa <tomasz.figa@gmail.com> 22 - External GPIO interrupts (see interrupts property in pin controller node); 24 - External wake-up interrupts - multiplexed (capable of waking up the system 25 see interrupts property in external wake-up interrupt controller node - 26 samsung,pinctrl-wakeup-interrupt.yaml); [all …]
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/linux/drivers/gpio/ |
H A D | gpio-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Xilinx Zynq GPIO device driver 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 10 #include <linux/gpio/driver.h> 20 #define DRIVER_NAME "zynq-gpio" 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) [all …]
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H A D | gpio-npcm-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Nuvoton NPCM Serial GPIO Driver 10 #include <linux/gpio/driver.h> 137 static void __iomem *bank_reg(struct npcm_sgpio *gpio, in bank_reg() argument 138 const struct npcm_sgpio_bank *bank, in bank_reg() argument 143 return gpio->base + bank->rdata_reg; in bank_reg() 145 return gpio->base + bank->wdata_reg; in bank_reg() 147 return gpio->base + bank->event_config; in bank_reg() 149 return gpio->base + bank->event_status; in bank_reg() 152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg() [all …]
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H A D | gpio-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Broadcom Kona GPIO Driver 5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com> 6 * Copyright (C) 2012-2014 Broadcom Corporation 11 #include <linux/gpio/driver.h> 24 #define GPIO_BANK(gpio) ((gpio) >> 5) argument 25 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) argument 27 /* There is a GPIO control register for each GPIO */ 28 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) argument 30 /* The remaining registers are per GPIO bank */ [all …]
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H A D | gpio-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only 13 #include <linux/gpio/driver.h> 22 #include <linux/pinctrl/pinconf-generic.h> 27 #include "../pinctrl/pinctrl-rockchip.h" 31 * Bits [31:24] - Major Version 32 * Bits [23:16] - Minor Version 33 * Bits [15:0] - Revision Number 35 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument 86 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel() [all …]
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H A D | gpio-davinci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * TI DaVinci GPIO Support 5 * Copyright (c) 2006-2007 David Brownell 9 #include <linux/gpio/driver.h> 43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 57 /* Serialize access to GPIO registers */ 66 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument 68 return 1 << (gpio % 32); in __gpio_mask() 82 /*--------------------------------------------------------------------------*/ 84 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ [all …]
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H A D | gpio-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * AppliedMicro X-Gene SoC GPIO Driver 15 #include <linux/gpio/driver.h> 45 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get() 57 setval = ioread32(chip->base + bank_offset); in __xgene_gpio_set() 62 iowrite32(setval, chip->base + bank_offset); in __xgene_gpio_set() 70 spin_lock_irqsave(&chip->lock, flags); in xgene_gpio_set() 72 spin_unlock_irqrestore(&chip->lock, flags); in xgene_gpio_set() 83 if (ioread32(chip->base + bank_offset) & BIT(bit_offset)) in xgene_gpio_get_direction() 98 spin_lock_irqsave(&chip->lock, flags); in xgene_gpio_dir_in() [all …]
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/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 interrupt-parent = <&gic>; 21 #interrupt-cells = <2>; [all …]
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H A D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \ 32 gpa0: gpa0-gpio-bank { 33 gpio-controller; [all …]
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H A D | exynos850-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 gpa0: gpa0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 20 interrupt-controller; 21 #interrupt-cells = <2>; [all …]
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
H A D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined, 2 this information will be used to translate gpio-specifiers. 10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", 11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", 12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" 13 - #gpio-cells : Should be two. The first cell is the pin number and the 15 - gpio-controller : Marks the port as GPIO controller. 17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C 20 - interrupts : This property provides the list of interrupt for each GPIO having 21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as [all …]
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/linux/arch/arm64/boot/dts/exynos/google/ |
H A D | gs101-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * GS101 SoC pin-mux and pin-config device tree source 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 9 #include "gs101-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 15 interrupt-controller; 16 #interrupt-cells = <2>; [all …]
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/linux/drivers/pinctrl/ |
H A D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Microsemi/Microchip SoCs serial gpio driver 13 #include <linux/gpio/driver.h> 107 static const char * const functions[] = { "gpio" }; 112 struct gpio_chip gpio; member 138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr() 139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr() 144 return bit + port * priv->bitcount; in sgpio_addr_to_pin() 149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr() 150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr() [all …]
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/linux/drivers/pinctrl/nuvoton/ |
H A D | pinctrl-ma35.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Author: Shan-Chun Hung <schung@nuvoton.com> 13 #include <linux/gpio/driver.h> 24 #include "pinctrl-ma35.h" 33 /* GPIO control registers */ 50 /* GPIO mode control */ 59 /* GPIO pull-up and pull-down selection control */ 66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger, 67 * while bits 16 ~ 31 control high-level or rising edge trigger. 84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ [all …]
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