Lines Matching +full:gpio +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
63 /* Register offsets for the GPIO device */
64 /* LSW Mask & Data -WO */
65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) argument
66 /* MSW Mask & Data -WO */
67 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) argument
68 /* Data Register-RW */
69 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) argument
70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) argument
71 /* Direction mode reg-RW */
72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) argument
73 /* Output enable reg-RW */
74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) argument
75 /* Interrupt mask reg-RO */
76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) argument
77 /* Interrupt enable reg-WO */
78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) argument
79 /* Interrupt disable reg-WO */
80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) argument
81 /* Interrupt status reg-RO */
82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) argument
83 /* Interrupt type reg-RW */
84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) argument
85 /* Interrupt polarity reg-RW */
86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) argument
87 /* Interrupt on any, reg-RW */
88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) argument
93 /* Mid pin number of a bank */
96 /* GPIO upper 16 bit mask */
117 * struct zynq_gpio - gpio device private data structure
119 * @base_addr: base address of the GPIO device
121 * @irq: interrupt for the GPIO device
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
159 * @gpio: Pointer to driver data struct
163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) in zynq_gpio_is_zynq() argument
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); in zynq_gpio_is_zynq()
169 * gpio_data_ro_bug - test if HW bug exists or not
170 * @gpio: Pointer to driver data struct
174 static int gpio_data_ro_bug(struct zynq_gpio *gpio) in gpio_data_ro_bug() argument
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); in gpio_data_ro_bug()
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
187 * @gpio: gpio device data structure
189 * Returns the bank number and pin offset within the bank.
194 struct zynq_gpio *gpio) in zynq_gpio_get_bank_pin() argument
196 int bank; in zynq_gpio_get_bank_pin() local
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
199 if ((pin_num >= gpio->p_data->bank_min[bank]) && in zynq_gpio_get_bank_pin()
200 (pin_num <= gpio->p_data->bank_max[bank])) { in zynq_gpio_get_bank_pin()
201 *bank_num = bank; in zynq_gpio_get_bank_pin()
202 *bank_pin_num = pin_num - in zynq_gpio_get_bank_pin()
203 gpio->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_get_bank_pin()
207 bank = bank + VERSAL_UNUSED_BANKS; in zynq_gpio_get_bank_pin()
211 WARN(true, "invalid GPIO pin number: %u", pin_num); in zynq_gpio_get_bank_pin()
217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
219 * @pin: gpio pin number within the device
221 * This function reads the state of the specified pin of the GPIO device.
229 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_get_value() local
231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_value()
233 if (gpio_data_ro_bug(gpio)) { in zynq_gpio_get_value()
234 if (zynq_gpio_is_zynq(gpio)) { in zynq_gpio_get_value()
236 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
244 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
252 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
259 * zynq_gpio_set_value - Modify the state of the pin with specified value
261 * @pin: gpio pin number within the device
266 * gpio pin to the specified value. The state is either 0 or non-zero.
272 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_set_value() local
274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_value()
278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; in zynq_gpio_set_value()
292 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
296 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
298 * @pin: gpio pin number within the device
300 * This function uses the read-modify-write sequence to set the direction of
301 * the gpio pin as input.
310 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_in() local
312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_in()
315 * On zynq bank 0 pins 7 and 8 are special and cannot be used in zynq_gpio_dir_in()
318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && in zynq_gpio_dir_in()
320 return -EINVAL; in zynq_gpio_dir_in()
323 spin_lock_irqsave(&gpio->dirlock, flags); in zynq_gpio_dir_in()
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
327 spin_unlock_irqrestore(&gpio->dirlock, flags); in zynq_gpio_dir_in()
333 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
335 * @pin: gpio pin number within the device
338 * This function sets the direction of specified GPIO pin as output, configures
350 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_out() local
352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_out()
354 /* set the GPIO pin as output */ in zynq_gpio_dir_out()
355 spin_lock_irqsave(&gpio->dirlock, flags); in zynq_gpio_dir_out()
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
364 spin_unlock_irqrestore(&gpio->dirlock, flags); in zynq_gpio_dir_out()
372 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
374 * @pin: gpio pin number within the device
376 * This function returns the direction of the specified GPIO.
384 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_get_direction() local
386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_direction()
388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_direction()
397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
400 * This function calculates gpio pin number from irq number and sets the
401 * bit in the Interrupt Disable register of the corresponding bank to disable
409 struct zynq_gpio *gpio = in zynq_gpio_irq_mask() local
413 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_mask()
414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_mask()
416 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
420 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
421 * @irq_data: irq data containing irq number of gpio pin for the interrupt
424 * This function calculates the gpio pin number from irq number and sets the
425 * bit in the Interrupt Enable register of the corresponding bank to enable
433 struct zynq_gpio *gpio = in zynq_gpio_irq_unmask() local
437 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_unmask()
438 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_unmask()
440 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
444 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
445 * @irq_data: irq data containing irq number of gpio pin for the interrupt
448 * This function calculates gpio pin number from irq number and sets the bit
449 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
454 struct zynq_gpio *gpio = in zynq_gpio_irq_ack() local
457 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_ack()
458 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_ack()
460 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
464 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
465 * @irq_data: irq data containing irq number of gpio pin for the interrupt
473 * The Zynq GPIO controller does not disable interrupt detection when in zynq_gpio_irq_enable()
487 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
488 * @irq_data: irq data containing irq number of gpio pin
489 * @type: interrupt type that is to be set for the gpio pin
491 * This function gets the gpio pin number and its bank from the gpio pin number
495 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
496 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
497 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
498 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
499 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
505 struct zynq_gpio *gpio = in zynq_gpio_set_irq_type() local
508 device_pin_num = irq_data->hwirq; in zynq_gpio_set_irq_type()
509 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_irq_type()
511 int_type = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
513 int_pol = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
515 int_any = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
546 return -EINVAL; in zynq_gpio_set_irq_type()
550 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
552 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
554 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
570 struct zynq_gpio *gpio = in zynq_gpio_set_wake() local
573 irq_set_irq_wake(gpio->irq, on); in zynq_gpio_set_wake()
583 ret = pm_runtime_resume_and_get(chip->parent); in zynq_gpio_irq_reqres()
587 return gpiochip_reqres_irq(chip, d->hwirq); in zynq_gpio_irq_reqres()
594 gpiochip_relres_irq(chip, d->hwirq); in zynq_gpio_irq_relres()
595 pm_runtime_put(chip->parent); in zynq_gpio_irq_relres()
626 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, in zynq_gpio_handle_bank_irq() argument
630 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; in zynq_gpio_handle_bank_irq()
631 struct irq_domain *irqdomain = gpio->chip.irq.domain; in zynq_gpio_handle_bank_irq()
642 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
645 * This function reads the Interrupt Status Register of each bank to get the
646 * gpio pin number which has triggered an interrupt. It then acks the triggered
649 * Note: A bug is reported if no handler is set for the gpio pin.
655 struct zynq_gpio *gpio = in zynq_gpio_irqhandler() local
661 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_irqhandler()
662 int_sts = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
664 int_enb = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
666 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); in zynq_gpio_irqhandler()
667 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_irqhandler()
674 static void zynq_gpio_save_context(struct zynq_gpio *gpio) in zynq_gpio_save_context() argument
678 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_save_context()
679 gpio->context.datalsw[bank_num] = in zynq_gpio_save_context()
680 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
682 gpio->context.datamsw[bank_num] = in zynq_gpio_save_context()
683 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
685 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
687 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
689 gpio->context.int_type[bank_num] = in zynq_gpio_save_context()
690 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
692 gpio->context.int_polarity[bank_num] = in zynq_gpio_save_context()
693 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
695 gpio->context.int_any[bank_num] = in zynq_gpio_save_context()
696 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
698 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_save_context()
703 static void zynq_gpio_restore_context(struct zynq_gpio *gpio) in zynq_gpio_restore_context() argument
707 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_restore_context()
708 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_restore_context()
710 writel_relaxed(gpio->context.datalsw[bank_num], in zynq_gpio_restore_context()
711 gpio->base_addr + in zynq_gpio_restore_context()
713 writel_relaxed(gpio->context.datamsw[bank_num], in zynq_gpio_restore_context()
714 gpio->base_addr + in zynq_gpio_restore_context()
716 writel_relaxed(gpio->context.dirm[bank_num], in zynq_gpio_restore_context()
717 gpio->base_addr + in zynq_gpio_restore_context()
719 writel_relaxed(gpio->context.int_type[bank_num], in zynq_gpio_restore_context()
720 gpio->base_addr + in zynq_gpio_restore_context()
722 writel_relaxed(gpio->context.int_polarity[bank_num], in zynq_gpio_restore_context()
723 gpio->base_addr + in zynq_gpio_restore_context()
725 writel_relaxed(gpio->context.int_any[bank_num], in zynq_gpio_restore_context()
726 gpio->base_addr + in zynq_gpio_restore_context()
728 writel_relaxed(~(gpio->context.int_en[bank_num]), in zynq_gpio_restore_context()
729 gpio->base_addr + in zynq_gpio_restore_context()
731 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_restore_context()
738 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_suspend() local
739 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_suspend()
743 return -EINVAL; in zynq_gpio_suspend()
747 disable_irq(gpio->irq); in zynq_gpio_suspend()
750 zynq_gpio_save_context(gpio); in zynq_gpio_suspend()
759 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_resume() local
760 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_resume()
765 return -EINVAL; in zynq_gpio_resume()
769 enable_irq(gpio->irq); in zynq_gpio_resume()
773 zynq_gpio_restore_context(gpio); in zynq_gpio_resume()
782 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_runtime_suspend() local
784 clk_disable_unprepare(gpio->clk); in zynq_gpio_runtime_suspend()
791 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_runtime_resume() local
793 return clk_prepare_enable(gpio->clk); in zynq_gpio_runtime_resume()
800 ret = pm_runtime_get_sync(chip->parent); in zynq_gpio_request()
811 pm_runtime_put(chip->parent); in zynq_gpio_free()
828 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
838 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
840 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
842 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
880 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
881 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
882 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
883 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
889 * zynq_gpio_probe - Initialization method for a zynq_gpio device
892 * This function allocates memory resources for the gpio device and registers
893 * all the banks of the device. It will also set up interrupts for the gpio
902 struct zynq_gpio *gpio; in zynq_gpio_probe() local
907 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in zynq_gpio_probe()
908 if (!gpio) in zynq_gpio_probe()
909 return -ENOMEM; in zynq_gpio_probe()
911 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); in zynq_gpio_probe()
913 dev_err(&pdev->dev, "of_match_node() failed\n"); in zynq_gpio_probe()
914 return -EINVAL; in zynq_gpio_probe()
916 gpio->p_data = match->data; in zynq_gpio_probe()
917 platform_set_drvdata(pdev, gpio); in zynq_gpio_probe()
919 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); in zynq_gpio_probe()
920 if (IS_ERR(gpio->base_addr)) in zynq_gpio_probe()
921 return PTR_ERR(gpio->base_addr); in zynq_gpio_probe()
923 gpio->irq = platform_get_irq(pdev, 0); in zynq_gpio_probe()
924 if (gpio->irq < 0) in zynq_gpio_probe()
925 return gpio->irq; in zynq_gpio_probe()
927 /* configure the gpio chip */ in zynq_gpio_probe()
928 chip = &gpio->chip; in zynq_gpio_probe()
929 chip->label = gpio->p_data->label; in zynq_gpio_probe()
930 chip->owner = THIS_MODULE; in zynq_gpio_probe()
931 chip->parent = &pdev->dev; in zynq_gpio_probe()
932 chip->get = zynq_gpio_get_value; in zynq_gpio_probe()
933 chip->set = zynq_gpio_set_value; in zynq_gpio_probe()
934 chip->request = zynq_gpio_request; in zynq_gpio_probe()
935 chip->free = zynq_gpio_free; in zynq_gpio_probe()
936 chip->direction_input = zynq_gpio_dir_in; in zynq_gpio_probe()
937 chip->direction_output = zynq_gpio_dir_out; in zynq_gpio_probe()
938 chip->get_direction = zynq_gpio_get_direction; in zynq_gpio_probe()
939 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); in zynq_gpio_probe()
940 chip->ngpio = gpio->p_data->ngpio; in zynq_gpio_probe()
942 /* Retrieve GPIO clock */ in zynq_gpio_probe()
943 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in zynq_gpio_probe()
944 if (IS_ERR(gpio->clk)) in zynq_gpio_probe()
945 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n"); in zynq_gpio_probe()
947 spin_lock_init(&gpio->dirlock); in zynq_gpio_probe()
949 pm_runtime_set_active(&pdev->dev); in zynq_gpio_probe()
950 pm_runtime_enable(&pdev->dev); in zynq_gpio_probe()
951 ret = pm_runtime_resume_and_get(&pdev->dev); in zynq_gpio_probe()
956 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_probe()
957 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_probe()
959 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_probe()
963 /* Set up the GPIO irqchip */ in zynq_gpio_probe()
964 girq = &chip->irq; in zynq_gpio_probe()
966 girq->parent_handler = zynq_gpio_irqhandler; in zynq_gpio_probe()
967 girq->num_parents = 1; in zynq_gpio_probe()
968 girq->parents = devm_kcalloc(&pdev->dev, 1, in zynq_gpio_probe()
969 sizeof(*girq->parents), in zynq_gpio_probe()
971 if (!girq->parents) { in zynq_gpio_probe()
972 ret = -ENOMEM; in zynq_gpio_probe()
975 girq->parents[0] = gpio->irq; in zynq_gpio_probe()
976 girq->default_type = IRQ_TYPE_NONE; in zynq_gpio_probe()
977 girq->handler = handle_level_irq; in zynq_gpio_probe()
979 /* report a bug if gpio chip registration fails */ in zynq_gpio_probe()
980 ret = gpiochip_add_data(chip, gpio); in zynq_gpio_probe()
982 dev_err(&pdev->dev, "Failed to add gpio chip\n"); in zynq_gpio_probe()
986 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY); in zynq_gpio_probe()
987 device_init_wakeup(&pdev->dev, 1); in zynq_gpio_probe()
988 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
993 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
995 pm_runtime_disable(&pdev->dev); in zynq_gpio_probe()
1001 * zynq_gpio_remove - Driver removal function
1008 struct zynq_gpio *gpio = platform_get_drvdata(pdev); in zynq_gpio_remove() local
1011 ret = pm_runtime_get_sync(&pdev->dev); in zynq_gpio_remove()
1013 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n"); in zynq_gpio_remove()
1014 gpiochip_remove(&gpio->chip); in zynq_gpio_remove()
1015 device_set_wakeup_capable(&pdev->dev, 0); in zynq_gpio_remove()
1016 pm_runtime_disable(&pdev->dev); in zynq_gpio_remove()
1032 MODULE_DESCRIPTION("Zynq GPIO driver");