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/linux/arch/arc/boot/dts/
H A Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
30 /* Port 1 */
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
[all …]
H A Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
30 /* Port 1 */
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-yosemite4.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,yosemite4-bmc", "aspeed,ast2600";
44 stdout-path = "serial4:57600n8";
52 reserved-memory {
53 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
12 #include <asm/mach-au1x00/au1000.h>
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
43 struct gpio;
45 static inline int au1000_gpio1_to_irq(int gpio) in au1000_gpio1_to_irq() argument
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1000_gpio1_to_irq()
50 static inline int au1000_gpio2_to_irq(int gpio) in au1000_gpio2_to_irq() argument
[all …]
/linux/drivers/ssb/
H A Ddriver_gpio.c3 * GPIO driver
6 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
13 #include <linux/gpio/driver.h>
26 static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned int gpio) in ssb_gpio_to_irq() argument
30 if (bus->bustype == SSB_BUSTYPE_SSB) in ssb_gpio_to_irq()
31 return irq_find_mapping(bus->irq_domain, gpio); in ssb_gpio_to_irq()
33 return -EINVAL; in ssb_gpio_to_irq()
41 static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned int gpio) in ssb_gpio_chipco_get_value() argument
45 return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); in ssb_gpio_chipco_get_value()
48 static int ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned int gpio, in ssb_gpio_chipco_set_value() argument
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
[all …]
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
163 zynq_gpio_is_zynq(struct zynq_gpio * gpio) zynq_gpio_is_zynq() argument
174 gpio_data_ro_bug(struct zynq_gpio * gpio) gpio_data_ro_bug() argument
194 zynq_gpio_get_bank_pin(unsigned int pin_num,unsigned int * bank_num,unsigned int * bank_pin_num,struct zynq_gpio * gpio) zynq_gpio_get_bank_pin() argument
229 struct zynq_gpio *gpio = gpiochip_get_data(chip); zynq_gpio_get_value() local
272 struct zynq_gpio *gpio = gpiochip_get_data(chip); zynq_gpio_set_value() local
312 struct zynq_gpio *gpio = gpiochip_get_data(chip); zynq_gpio_dir_in() local
352 struct zynq_gpio *gpio = gpiochip_get_data(chip); zynq_gpio_dir_out() local
386 struct zynq_gpio *gpio = gpiochip_get_data(chip); zynq_gpio_get_direction() local
411 struct zynq_gpio *gpio = zynq_gpio_irq_mask() local
435 struct zynq_gpio *gpio = zynq_gpio_irq_unmask() local
456 struct zynq_gpio *gpio = zynq_gpio_irq_ack() local
507 struct zynq_gpio *gpio = zynq_gpio_set_irq_type() local
572 struct zynq_gpio *gpio = zynq_gpio_set_wake() local
628 zynq_gpio_handle_bank_irq(struct zynq_gpio * gpio,unsigned int bank_num,unsigned long pending) zynq_gpio_handle_bank_irq() argument
657 struct zynq_gpio *gpio = zynq_gpio_irqhandler() local
676 zynq_gpio_save_context(struct zynq_gpio * gpio) zynq_gpio_save_context() argument
705 zynq_gpio_restore_context(struct zynq_gpio * gpio) zynq_gpio_restore_context() argument
740 struct zynq_gpio *gpio = dev_get_drvdata(dev); zynq_gpio_suspend() local
761 struct zynq_gpio *gpio = dev_get_drvdata(dev); zynq_gpio_resume() local
784 struct zynq_gpio *gpio = dev_get_drvdata(dev); zynq_gpio_runtime_suspend() local
793 struct zynq_gpio *gpio = dev_get_drvdata(dev); zynq_gpio_runtime_resume() local
904 struct zynq_gpio *gpio; zynq_gpio_probe() local
1010 struct zynq_gpio *gpio = platform_get_drvdata(pdev); zynq_gpio_remove() local
[all...]
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
33 /* Non-constan
256 aspeed_gpio_g4_bank_reg(struct aspeed_gpio * gpio,const struct aspeed_gpio_bank * bank,const enum aspeed_gpio_reg reg) aspeed_gpio_g4_bank_reg() argument
342 find_bank_props(struct aspeed_gpio * gpio,unsigned int offset) find_bank_props() argument
355 have_gpio(struct aspeed_gpio * gpio,unsigned int offset) have_gpio() argument
365 have_input(struct aspeed_gpio * gpio,unsigned int offset) have_input() argument
375 have_output(struct aspeed_gpio * gpio,unsigned int offset) have_output() argument
382 aspeed_gpio_change_cmd_source(struct aspeed_gpio * gpio,unsigned int offset,int cmdsrc) aspeed_gpio_change_cmd_source() argument
388 aspeed_gpio_copro_request(struct aspeed_gpio * gpio,unsigned int offset) aspeed_gpio_copro_request() argument
397 aspeed_gpio_copro_release(struct aspeed_gpio * gpio,unsigned int offset) aspeed_gpio_copro_release() argument
404 aspeed_gpio_support_copro(struct aspeed_gpio * gpio) aspeed_gpio_support_copro() argument
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_get() local
420 struct aspeed_gpio *gpio = gpiochip_get_data(gc); __aspeed_gpio_set() local
429 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_set() local
446 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_dir_in() local
465 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_dir_out() local
485 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_get_direction() local
502 irqd_to_aspeed_gpio_data(struct irq_data * d,struct aspeed_gpio ** gpio,int * offset) irqd_to_aspeed_gpio_data() argument
522 struct aspeed_gpio *gpio; aspeed_gpio_irq_ack() local
542 struct aspeed_gpio *gpio; aspeed_gpio_irq_set_mask() local
584 struct aspeed_gpio *gpio; aspeed_gpio_set_type() local
638 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_gpio_irq_handler() local
657 struct aspeed_gpio *gpio = gpiochip_get_data(gc); aspeed_init_irq_valid_mask() local
681 struct aspeed_gpio *gpio = gpiochip_get_data(chip); aspeed_gpio_reset_tolerance() local
709 usecs_to_cycles(struct aspeed_gpio * gpio,unsigned long usecs,u32 * cycles) usecs_to_cycles() argument
733 register_allocated_timer(struct aspeed_gpio * gpio,unsigned int offset,unsigned int timer) register_allocated_timer() argument
752 unregister_allocated_timer(struct aspeed_gpio * gpio,unsigned int offset) unregister_allocated_timer() argument
771 timer_allocation_registered(struct aspeed_gpio * gpio,unsigned int offset) timer_allocation_registered() argument
778 configure_timer(struct aspeed_gpio * gpio,unsigned int offset,unsigned int timer) configure_timer() argument
791 struct aspeed_gpio *gpio = gpiochip_get_data(chip); enable_debounce() local
868 struct aspeed_gpio *gpio = gpiochip_get_data(chip); disable_debounce() local
883 struct aspeed_gpio *gpio = gpiochip_get_data(chip); set_debounce() local
944 struct aspeed_gpio *gpio = gpiochip_get_data(chip); aspeed_gpio_copro_grab_gpio() local
989 struct aspeed_gpio *gpio = gpiochip_get_data(chip); aspeed_gpio_copro_release_gpio() local
1021 struct aspeed_gpio *gpio; aspeed_gpio_irq_print_chip() local
1041 aspeed_g4_reg_bit_set(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg,bool val) aspeed_g4_reg_bit_set() argument
1063 aspeed_g4_reg_bit_get(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg) aspeed_g4_reg_bit_get() argument
1072 aspeed_g4_reg_bank_get(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg) aspeed_g4_reg_bank_get() argument
1084 aspeed_g4_privilege_ctrl(struct aspeed_gpio * gpio,unsigned int offset,int cmdsrc) aspeed_g4_privilege_ctrl() argument
1096 aspeed_g4_privilege_init(struct aspeed_gpio * gpio) aspeed_g4_privilege_init() argument
1109 aspeed_g4_copro_request(struct aspeed_gpio * gpio,unsigned int offset) aspeed_g4_copro_request() argument
1130 aspeed_g4_copro_release(struct aspeed_gpio * gpio,unsigned int offset) aspeed_g4_copro_release() argument
1156 aspeed_g7_reg_bit_set(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg,bool val) aspeed_g7_reg_bit_set() argument
1169 aspeed_g7_reg_bit_get(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg) aspeed_g7_reg_bit_get() argument
1185 aspeed_g7_reg_bank_get(struct aspeed_gpio * gpio,unsigned int offset,const enum aspeed_gpio_reg reg) aspeed_g7_reg_bank_get() argument
1311 struct aspeed_gpio *gpio; aspeed_gpio_probe() local
[all...]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
21 mpp3 3 gpio, i2c0(sda)
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l45.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
26 maxItems: 1
29 maxItems: 1
31 '#sound-dai-cells':
[all …]
/linux/arch/mips/boot/dts/pic32/
H A Dpic32mzda.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/microchip,pic32-clock.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&evic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
43 compatible = "microchip,pic32mzda-infra";
49 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dmrvl-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
12 - Rob Herring <robh@kernel.org>
15 - if:
20 - intel,pxa25x-gpio
[all …]
H A Drenesas,rcar-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,gpio-r8a7778 # R-Car M1
18 - renesas,gpio-r8a7779 # R-Car H1
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #define MFP_PIN_PXA300(gpio) \ argument
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
11 #define MFP_PIN_PXA300_2(gpio) \ argument
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
16 #define MFP_PIN_PXA310(gpio) \ argument
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-ac5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "pinctrl-mvebu.h"
21 MPP_FUNCTION(0, "gpio", NULL),
22 MPP_FUNCTION(1, "sdio", "d0"),
24 MPP_MODE(1,
25 MPP_FUNCTION(0, "gpio", NULL),
26 MPP_FUNCTION(1, "sdio", "d1"),
29 MPP_FUNCTION(0, "gpio", NULL),
30 MPP_FUNCTION(1, "sdio", "d2"),
33 MPP_FUNCTION(0, "gpio", NULL),
[all …]
/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
26 * is 1.
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dbase.c29 nvkm_gpio_drive(struct nvkm_gpio *gpio, int idx, int line, int dir, int out) in nvkm_gpio_drive() argument
31 return gpio->func->drive(gpio, line, dir, out); in nvkm_gpio_drive()
35 nvkm_gpio_sense(struct nvkm_gpio *gpio, int idx, int line) in nvkm_gpio_sense() argument
37 return gpio->func->sense(gpio, line); in nvkm_gpio_sense()
41 nvkm_gpio_reset(struct nvkm_gpio *gpio, u8 func) in nvkm_gpio_reset() argument
43 if (gpio->func->reset) in nvkm_gpio_reset()
44 gpio->func->reset(gpio, func); in nvkm_gpio_reset()
48 nvkm_gpio_find(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line, in nvkm_gpio_find() argument
51 struct nvkm_device *device = gpio->subdev.device; in nvkm_gpio_find()
52 struct nvkm_bios *bios = device->bios; in nvkm_gpio_find()
[all …]
/linux/drivers/bcma/
H A Ddriver_gpio.c3 * GPIO driver
6 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
11 #include <linux/gpio/driver.h>
22 static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) in bcma_gpio_get_value() argument
26 return !!bcma_chipco_gpio_in(cc, 1 << gpio); in bcma_gpio_get_value()
29 static int bcma_gpio_set_value(struct gpio_chip *chip, unsigned int gpio, in bcma_gpio_set_value() argument
34 bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); in bcma_gpio_set_value()
39 static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) in bcma_gpio_direction_input() argument
43 bcma_chipco_gpio_outen(cc, 1 << gpio, 0); in bcma_gpio_direction_input()
47 static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, in bcma_gpio_direction_output() argument
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
146 [FUNC_GPIO] = "gpio",
240 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
241 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
242 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
243 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admfm2000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kim Seer Paller <kimseer.paller@analog.com>
22 - adi,admfm2000
24 '#address-cells':
25 const: 1
27 '#size-cells':
31 "^channel@[0-1]$":
42 maximum: 1
[all …]

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