| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx.c | 39 /* delay 0.1 second to enable gfx off feature */
45 * GPU GFX IP block helpers function.
53 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
54 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
55 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
64 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
65 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
66 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
67 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
68 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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| H A D | gfx_v11_0.c | 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
262 /* gfx queue registers */
362 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
427 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
496 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
673 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
674 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
675 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
676 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
678 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
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| H A D | gfx_v12_0.c | 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
208 /* gfx queue registers */
357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
557 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
558 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
559 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
560 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
562 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v12_0_init_microcode()
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| H A D | gfx_v12_1.c | 41 #include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h"
157 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_1_kiq_unmap_queues()
228 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_set_kiq_pm4_funcs()
230 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; in gfx_v12_1_set_kiq_pm4_funcs()
370 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_1_free_microcode()
371 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_1_free_microcode()
373 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_1_free_microcode()
412 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_1_init_microcode()
417 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v12_1_init_microcode()
425 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v12_1_init_microcode()
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| H A D | gfx_v6_0.c | 353 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
362 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v6_0_init_microcode()
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
368 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
369 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
371 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v6_0_init_microcode()
376 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
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| H A D | gfx_v9_0.c | 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
934 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_0_kiq_set_resources()
1093 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1283 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1284 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1285 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1286 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1287 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1288 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1290 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
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| H A D | amdgpu_kms.c | 237 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
238 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
241 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
242 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
245 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
246 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
249 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
250 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
253 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
254 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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| H A D | amdgpu_dev_coredump.c | 96 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
98 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
100 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
102 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
105 adev->gfx.rlc_srlc_feature_version, in amdgpu_devcoredump_fw_info()
106 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
108 adev->gfx.rlc_srlg_feature_version, in amdgpu_devcoredump_fw_info()
109 adev->gfx.rlc_srlg_fw_version); in amdgpu_devcoredump_fw_info()
111 adev->gfx.rlc_srls_feature_version, in amdgpu_devcoredump_fw_info()
112 adev->gfx.rlc_srls_fw_version); in amdgpu_devcoredump_fw_info()
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| H A D | imu_v12_0.c | 52 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
55 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
60 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_init_microcode()
61 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v12_0_init_microcode()
66 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
71 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
81 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v12_0_init_microcode()
93 if (!adev->gfx.imu_fw) in imu_v12_0_load_microcode()
96 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_load_microcode()
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v12_0_load_microcode()
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| H A D | amdgpu_discovery.c | 847 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1136 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1486 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1586 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1744 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1745 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1747 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1748 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1749 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1750 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
102 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n", in set_pasid_vmid_mapping_v10_3()
115 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
116 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
197 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
198 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3()
289 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
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| H A D | amdgpu_amdkfd.c | 183 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
184 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
197 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
204 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
205 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
476 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
479 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
482 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
485 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
488 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
98 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n", in set_pasid_vmid_mapping_v11()
111 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v11()
112 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v11()
182 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v11()
183 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v11()
265 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v11()
274 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v11()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_acquire_queue()
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_acquire_queue()
75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
115 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
166 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
167 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
305 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load()
314 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
315 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
320 spin_lock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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| H A D | amdgpu_cgs.c | 173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intel-i915-hwmon | 4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu_v13_0_1_ppsmc.h | 55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
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| H A D | smu_v13_0_4_ppsmc.h | 65 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
70 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
76 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
78 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
82 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
83 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
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| H A D | smu_v13_0_5_ppsmc.h | 45 #define PPSMC_MSG_GfxDeviceDriverReset 10 ///< Request GFX mode 2 reset
50 #define PPSMC_MSG_GetGfxclkFrequency 15 ///< Get GFX clock frequency
56 #define PPSMC_MSG_SetHardMinGfxClk 21 ///< Set hard min for GFX CLK
61 #define PPSMC_MSG_PrepareMp1ForUnload 26 ///< Prepare PMFW for GFX driver unload
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| H A D | smu11_driver_if_sienna_cichlid.h | 249 // GFX GPO Feature Contains PACE and DEM sub features
452 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
655 …old; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnect…
716 // GFX GPO
731 …uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX D…
732 … DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase …
734 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
737 …imeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before …
837 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
1015 …old; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnect…
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| H A D | smu14_driver_if_v14_0.h | 817 //Gfx Vf Curve
819 //gfx Vmax
1079 //Expected GFX Duty Cycle at Vmax.
1158 //GFX Idle Power Settings
1163 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
1195 // GFX DCS
1198 …uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS…
1199 … DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase …
1201 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1204 …uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX i…
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_gfxpll.c | 15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
139 /* GFX (DC, GPU, GMC) PLL initialization and destroy function */
177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_crat.c | 1433 if (adev->gfx.config.gc_tcp_l1_size) { in kfd_fill_gpu_cache_info_from_gfx_config()
1434 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1439 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1440 pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1446 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1448 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
1453 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1454 pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1460 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1461 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
[all …]
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| /linux/drivers/gpu/drm/i915/gt/uc/abi/ |
| H A D | guc_klvs_abi.h | 42 * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.
46 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.
54 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.
58 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,gpucc.yaml | 59 vdd-gfx-supply:
68 # Require that power-domains and vdd-gfx-supply are not both present
72 - vdd-gfx-supply
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