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/linux/drivers/clk/at91/
H A Dclk-generated.c38 static int clk_generated_set(struct clk_generated *gck, int status) in clk_generated_set() argument
43 spin_lock_irqsave(gck->lock, flags); in clk_generated_set()
44 regmap_write(gck->regmap, gck->layout->offset, in clk_generated_set()
45 (gck->id & gck->layout->pid_mask)); in clk_generated_set()
46 regmap_update_bits(gck->regmap, gck->layout->offset, in clk_generated_set()
47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | in clk_generated_set()
48 gck->layout->cmd | enable, in clk_generated_set()
49 field_prep(gck->layout->gckcss_mask, gck->parent_id) | in clk_generated_set()
50 gck->layout->cmd | in clk_generated_set()
51 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | in clk_generated_set()
[all …]
/linux/drivers/clk/
H A Dclk-lan966x.c69 struct lan966x_gck *gck = to_lan966x_gck(hw); in lan966x_gck_enable() local
70 u32 val = readl(gck->reg); in lan966x_gck_enable()
73 writel(val, gck->reg); in lan966x_gck_enable()
80 struct lan966x_gck *gck = to_lan966x_gck(hw); in lan966x_gck_disable() local
81 u32 val = readl(gck->reg); in lan966x_gck_disable()
84 writel(val, gck->reg); in lan966x_gck_disable()
91 struct lan966x_gck *gck = to_lan966x_gck(hw); in lan966x_gck_set_rate() local
92 u32 div, val = readl(gck->reg); in lan966x_gck_set_rate()
101 writel(val, gck->reg); in lan966x_gck_set_rate()
109 struct lan966x_gck *gck = to_lan966x_gck(hw); in lan966x_gck_recalc_rate() local
[all …]
H A DKconfig264 This driver provides support for Generic Clock Controller(GCK) on
265 LAN966X SoC. GCK generates and supplies clock to various peripherals
/linux/drivers/mmc/host/
H A Dsdhci-of-at91.c47 struct clk *gck; member
181 gck_rate = clk_get_rate(priv->gck); in sdhci_at91_set_clks_presets()
201 dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", in sdhci_at91_set_clks_presets()
227 clk_prepare_enable(priv->gck); in sdhci_at91_set_clks_presets()
261 clk_disable_unprepare(priv->gck); in sdhci_at91_runtime_suspend()
296 ret = clk_prepare_enable(priv->gck); in sdhci_at91_runtime_resume()
298 dev_err(dev, "can't enable gck\n"); in sdhci_at91_runtime_resume()
352 priv->gck = devm_clk_get(&pdev->dev, "multclk"); in sdhci_at91_probe()
353 if (IS_ERR(priv->gck)) { in sdhci_at91_probe()
355 ret = PTR_ERR(priv->gck); in sdhci_at91_probe()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,lan966x-gck.yaml4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
19 const: microchip,lan966x-gck
54 compatible = "microchip,lan966x-gck";
H A Datmel,at91rm9200-pmc.yaml62 gck and programmable clocks).
/linux/Documentation/devicetree/bindings/media/
H A Datmel,isc.yaml38 - const: gck
100 clock-names = "hclock", "iscck", "gck";
/linux/sound/soc/atmel/
H A Datmel-pdmic.c605 dev_err(dev, "failed to get GCK: %d\n", ret); in atmel_pdmic_probe()
614 dev_err(dev, "failed to set GCK clock rate: %d\n", ret); in atmel_pdmic_probe()
H A Datmel-classd.c555 dev_err(dev, "failed to get GCK clock: %d\n", ret); in atmel_classd_probe()
H A Dmchp-pdmc.c1044 dev_err(dev, "failed to get GCK: %d\n", ret); in mchp_pdmc_probe()
/linux/include/linux/clk/
H A Dat91_pmc.h251 #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x.dtsi64 compatible = "microchip,lan966x-gck";
H A Dsama5d2.dtsi255 clock-names = "hclock", "iscck", "gck";