154203301SEugen Hristev# SPDX-License-Identifier: GPL-2.0-only 254203301SEugen Hristev# Copyright (C) 2016-2021 Microchip Technology, Inc. 354203301SEugen Hristev%YAML 1.2 454203301SEugen Hristev--- 554203301SEugen Hristev$id: http://devicetree.org/schemas/media/atmel,isc.yaml# 654203301SEugen Hristev$schema: http://devicetree.org/meta-schemas/core.yaml# 754203301SEugen Hristev 854203301SEugen Hristevtitle: Atmel Image Sensor Controller (ISC) 954203301SEugen Hristev 1054203301SEugen Hristevmaintainers: 1154203301SEugen Hristev - Eugen Hristev <eugen.hristev@microchip.com> 1254203301SEugen Hristev 1354203301SEugen Hristevdescription: | 1454203301SEugen Hristev The Image Sensor Controller (ISC) device provides the video input capabilities for the 1554203301SEugen Hristev Atmel/Microchip AT91 SAMA family of devices. 1654203301SEugen Hristev 1754203301SEugen Hristev The ISC has a single parallel input that supports RAW Bayer, RGB or YUV video, 1854203301SEugen Hristev with both external synchronization and BT.656 synchronization for the latter. 1954203301SEugen Hristev 2054203301SEugen Hristevproperties: 2154203301SEugen Hristev compatible: 2254203301SEugen Hristev const: atmel,sama5d2-isc 2354203301SEugen Hristev 2454203301SEugen Hristev reg: 2554203301SEugen Hristev maxItems: 1 2654203301SEugen Hristev 2754203301SEugen Hristev interrupts: 2854203301SEugen Hristev maxItems: 1 2954203301SEugen Hristev 3054203301SEugen Hristev clocks: 3154203301SEugen Hristev minItems: 3 3254203301SEugen Hristev maxItems: 3 3354203301SEugen Hristev 3454203301SEugen Hristev clock-names: 3554203301SEugen Hristev items: 3654203301SEugen Hristev - const: hclock 3754203301SEugen Hristev - const: iscck 3854203301SEugen Hristev - const: gck 3954203301SEugen Hristev 4054203301SEugen Hristev '#clock-cells': 4154203301SEugen Hristev const: 0 4254203301SEugen Hristev 4354203301SEugen Hristev clock-output-names: 4454203301SEugen Hristev const: isc-mck 4554203301SEugen Hristev 4654203301SEugen Hristev port: 47db60b87eSRob Herring $ref: /schemas/graph.yaml#/$defs/port-base 48*0bf99c1fSRob Herring additionalProperties: false 4954203301SEugen Hristev description: 5054203301SEugen Hristev Input port node, single endpoint describing the input pad. 5154203301SEugen Hristev 5254203301SEugen Hristev properties: 5354203301SEugen Hristev endpoint: 5454203301SEugen Hristev $ref: video-interfaces.yaml# 5554203301SEugen Hristev 5654203301SEugen Hristev properties: 5754203301SEugen Hristev remote-endpoint: true 5854203301SEugen Hristev 5954203301SEugen Hristev bus-width: 6054203301SEugen Hristev enum: [8, 9, 10, 11, 12] 6154203301SEugen Hristev default: 12 6254203301SEugen Hristev 6354203301SEugen Hristev hsync-active: 6454203301SEugen Hristev enum: [0, 1] 6554203301SEugen Hristev default: 1 6654203301SEugen Hristev 6754203301SEugen Hristev vsync-active: 6854203301SEugen Hristev enum: [0, 1] 6954203301SEugen Hristev default: 1 7054203301SEugen Hristev 7154203301SEugen Hristev pclk-sample: 7254203301SEugen Hristev enum: [0, 1] 7354203301SEugen Hristev default: 1 7454203301SEugen Hristev 7554203301SEugen Hristev required: 7654203301SEugen Hristev - remote-endpoint 7754203301SEugen Hristev 7854203301SEugen Hristev additionalProperties: false 7954203301SEugen Hristev 8054203301SEugen Hristevrequired: 8154203301SEugen Hristev - compatible 8254203301SEugen Hristev - reg 8354203301SEugen Hristev - clocks 8454203301SEugen Hristev - clock-names 8554203301SEugen Hristev - '#clock-cells' 8654203301SEugen Hristev - clock-output-names 8754203301SEugen Hristev - port 8854203301SEugen Hristev 8954203301SEugen HristevadditionalProperties: false 9054203301SEugen Hristev 9154203301SEugen Hristevexamples: 9254203301SEugen Hristev - | 9354203301SEugen Hristev #include <dt-bindings/interrupt-controller/irq.h> 9454203301SEugen Hristev 9554203301SEugen Hristev isc: isc@f0008000 { 9654203301SEugen Hristev compatible = "atmel,sama5d2-isc"; 9754203301SEugen Hristev reg = <0xf0008000 0x4000>; 9854203301SEugen Hristev interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 9954203301SEugen Hristev clocks = <&isc_clk>, <&iscck>, <&isc_gclk>; 10054203301SEugen Hristev clock-names = "hclock", "iscck", "gck"; 10154203301SEugen Hristev #clock-cells = <0>; 10254203301SEugen Hristev clock-output-names = "isc-mck"; 10354203301SEugen Hristev 10454203301SEugen Hristev port { 10554203301SEugen Hristev isc_0: endpoint { 10654203301SEugen Hristev remote-endpoint = <&ov7740_0>; 10754203301SEugen Hristev hsync-active = <1>; 10854203301SEugen Hristev vsync-active = <0>; 10954203301SEugen Hristev pclk-sample = <1>; 11054203301SEugen Hristev bus-width = <8>; 11154203301SEugen Hristev }; 11254203301SEugen Hristev }; 11354203301SEugen Hristev }; 114