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Searched +full:gce +full:- +full:events (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-rsz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
19 - enum:
20 - mediatek,mt8183-mdp3-rsz
21 - items:
22 - enum:
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H A Dmediatek,mdp3-rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
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H A Dmediatek,mdp3-wrot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
19 - enum:
20 - mediatek,mt8183-mdp3-wrot
21 - items:
22 - enum:
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dmediatek,gce-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
14 single-core command dispatcher for MediaTek hardware. The Command Queue
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
17 and configure GCE to execute the specified instruction set in the message.
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
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/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmediatek,ccorr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
19 - enum:
20 - mediatek,mt8183-mdp3-ccorr
25 mediatek,gce-client-reg:
26 $ref: /schemas/types.yaml#/definitions/phandle-array
29 - description: phandle of GCE
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H A Dmediatek,wdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
20 - enum:
21 - mediatek,mt8183-mdp3-wdma
26 mediatek,gce-client-reg:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle of GCE
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H A Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
27 - mediatek,mt2701-disp-mutex
28 - mediatek,mt2712-disp-mutex
29 - mediatek,mt6795-disp-mutex
30 - mediatek,mt8167-disp-mutex
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/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
14 /* GCE thread priority */
27 /* GCE subsys table */
60 /* GCE General Purpose Register (GPR) support
63 /* GCE: write mask */
89 /* GCE hardware events */
349 * Following definitions are gce sw token which may use by clients
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
396 /* Resource lock event to control resource in GCE thread */
H A Dmt6779-gce.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
12 /* GCE HW thread priority */
22 /* GCE subsys table */
55 /* GCE hardware events */
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
29 * struct mtk_crtc - MediaTek specific crtc structure.
97 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_crtc_finish_page_flip()
100 if (mtk_crtc->event) { in mtk_crtc_finish_page_flip()
101 spin_lock_irqsave(&crtc->dev->event_lock, flags); in mtk_crtc_finish_page_flip()
102 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); in mtk_crtc_finish_page_flip()
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H A Dmtk_disp_ovl.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/soc/mediatek/mtk-cmdq.h>
51 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
52 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
53 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
77 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
79 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
156 * struct mtk_disp_ovl - DISP_OVL driver structure
157 * @crtc: associated crtc to report vblank events to
175 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); in mtk_disp_ovl_irq_handler()
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