| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
58 /** @brief clock recovered from EAVB input */
73 * @brief controls the EMC clock frequency.
74 * @details Doing a clk_set_rate on this clock will select the
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | maxim,max9485.txt | 1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, mus
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| H A D | altr_socfpga.txt | 1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
13 can get gated.
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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| H A D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6qdl-sr-som-ti.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
41 #include <dt-bindings/gpio/gpio.h>
44 nvcc_sd1: regulator-nvcc-sd1 {
45 compatible = "regulator-fixed";
46 regulator-always-on;
47 regulator-name = "nvcc_sd1";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 vin-supply = <&vcc_3v3>;
53 clk_ti_wifi: ti-wifi-clock {
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| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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| H A D | fpga-region.txt | 6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
44 * The size and specific location of each PRR is fixed.
45 * The connections at the edge of each PRR are fixed. The image that is loaded
48 branch that may be gated independentl
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mm-beacon-baseboard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
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| /freebsd/sys/riscv/sifive/ |
| H A D | sifive_prci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
85 #define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
86 #define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
87 #define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
88 #define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
101 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103 bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
164 /* FU540 clock numbers */
183 /* FU540 fixed divisor clock TLCLK. */
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3588-tiger.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
12 compatible = "tsd,rk3588-tiger", "rockchip,rk3588";
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc";
21 pinctrl-0 = <&emmc_reset>;
22 pinctrl-names = "default";
23 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
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| H A D | rk3588-jaguar.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/usb/pd.h>
15 model = "Theobroma Systems RK3588-SBC Jaguar";
16 compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
18 adc-keys {
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| H A D | rk3588-orangepi-5-plus.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/usb/pd.h>
17 compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
25 stdout-path = "serial2:1500000n8";
28 adc-keys-0 {
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| /freebsd/sys/contrib/device-tree/Bindings/arm/tegra/ |
| H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
48 #define AR5311_QDCLKGATE 0x005c /* QCU/DCU clock gating control */
62 /* Shadow copies with read-and-clear access */
148 #define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
149 #define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
150 #define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
151 #define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
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| /freebsd/sys/contrib/device-tree/Bindings/soc/tegra/ |
| H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
45 /* 0x5c is for QCU/DCU clock gating control on 5311 */
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
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| /freebsd/share/dict/ |
| H A D | web2a | 12 A-b-c book
13 A-b-c method
14 abdomino-uterotomy
15 Abdul-baha
16 a-be
20 able-bodied
21 able-bodiedness
22 able-minded
23 able-mindedness
27 Abor-miri
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| H A D | web2 | 37717 clock
70509 fixed
75858 gated
99810 Jean-Christophe
99811 Jean-Pierre
|
| /freebsd/crypto/openssl/ |
| H A D | CHANGES.md | 4 This is a detailed breakdown of significant changes. For a high-level overview
13 ----------------
15 - [OpenSSL 3.5](#openssl-35)
16 - [OpenSSL 3.4](#openssl-34)
17 - [OpenSSL 3.3](#openssl-33)
18 - [OpenSSL 3.2](#openssl-32)
19 - [OpenSSL 3.1](#openssl-31)
20 - [OpenSSL 3.0](#openssl-30)
21 - [OpenSSL 1.1.1](#openssl-111)
22 - [OpenSSL 1.1.0](#openssl-110)
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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| /freebsd/sys/dev/ixgbe/ |
| H A D | ixgbe_type.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * - IXGBE_ERROR_INVALID_STATE
48 * - IXGBE_ERROR_POLLING
53 * - IXGBE_ERROR_CAUTION
58 * - IXGBE_ERROR_SOFTWARE
64 * - IXGBE_ERROR_ARGUMENT
69 * - IXGBE_ERROR_UNSUPPORTED
170 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
427 (0x012300 + (((_i) - 24) * 4)))
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| /freebsd/sys/netinet/tcp_stacks/ |
| H A D | rack.c | 1 /*-
2 * Copyright (c) 2016-2020 Netflix, Inc.
159 * - Matt Mathis's Rate Halving which slowly drops
160 * the congestion window so that the ack clock can
162 * - Yuchung Cheng's RACK TCP (for which its named) that
165 * - Reorder Detection of RFC4737 and the Tail-Loss probe draft
183 * TCP output is also over-written with a new version since it
188 static int32_t rack_tlp_limit = 2; /* No more than 2 TLPs w-out new data */
191 static int32_t rack_reorder_fade = 60000000; /* 0 - never fade, def 60,000,000
192 * - 60 seconds */
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| /freebsd/contrib/sqlite3/ |
| H A D | sqlite3.c | 17 ** language. The code for the "sqlite3" command-line shell is also in a
20 ** The content in this amalgamation comes from Fossil check-in
54 ** NO_TEST - The branches on this line are not
59 ** OPTIMIZATION-IF-TRUE - This branch is allowed to always be false
63 ** OPTIMIZATION-IF-FALSE - This branch is allowed to always be true
67 ** PREVENTS-HARMLESS-OVERREAD - This branch prevents a buffer overread
72 ** slash-asterisk...asterisk-slash comment marks, with no spaces between the
147 ** 2015-03-02
185 ** large file support, or if the OS is windows, these should be no-ops.
191 ** Large file support can be disabled using the -DSQLITE_DISABLE_LFS switch
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