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/linux/Documentation/devicetree/bindings/clock/
H A Dgated-fixed-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gated Fixed clock
10 - Heiko Stuebner <heiko@sntech.de>
14 const: gated-fixed-clock
16 "#clock-cells":
19 clock-frequency: true
21 clock-output-names:
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H A Dvt8500.txt1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
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/linux/drivers/clk/
H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
9 * Gpio controlled clock implementation
12 #include <linux/clk-provider.h>
23 * DOC: basic gpio gated clock which can be enabled and disabled
25 * Traits of this clock:
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
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H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cortina Gemini SoC Clock Controller driver
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
54 * @bit_idx: the bit used to gate this clock in the clock register
55 * @name: the clock name
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H A Dclk-vt8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clock implementation for VIA/Wondermedia SoC's
13 #include <linux/clk-provider.h>
53 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc"); in vtwm_set_pmc_base()
81 spin_lock_irqsave(cdev->lock, flags); in vt8500_dclk_enable()
83 en_val = readl(cdev->en_reg); in vt8500_dclk_enable()
84 en_val |= BIT(cdev->en_bit); in vt8500_dclk_enable()
85 writel(en_val, cdev->en_reg); in vt8500_dclk_enable()
87 spin_unlock_irqrestore(cdev->lock, flags); in vt8500_dclk_enable()
97 spin_lock_irqsave(cdev->lock, flags); in vt8500_dclk_disable()
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/linux/arch/mips/bcm63xx/
H A Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
92 if (clk->id == 0) in enetx_set()
111 * Ethernet PHY clock
125 * Ethernet switch SAR clock
140 * Ethernet switch USB clock
155 * Ethernet switch clock
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/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
58 /** @brief clock recovered from EAVB input */
73 * @brief controls the EMC clock frequency.
74 * @details Doing a clk_set_rate on this clock will select the
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-edgeble-neu6a-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
11 stdout-path = "serial2:1500000n8";
14 hdmi1-con {
15 compatible = "hdmi-connector";
20 remote-endpoint = <&hdmi1_out_con>;
25 /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
26 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
27 compatible = "gated-fixed-clock";
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H A Drk3588-tiger.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "tsd,rk3588-tiger", "rockchip,rk3588";
21 emmc_pwrseq: emmc-pwrseq {
22 compatible = "mmc-pwrseq-emmc";
23 pinctrl-0 = <&emmc_reset>;
24 pinctrl-names = "default";
25 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
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H A Drk3588-jaguar.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
12 #include <dt-bindings/usb/pd.h>
17 model = "Theobroma Systems RK3588-SBC Jaguar";
18 compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
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H A Drk3588-orangepi-5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/usb/pd.h>
22 stdout-path = "serial2:1500000n8";
25 adc-keys-0 {
26 compatible = "adc-keys";
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/linux/drivers/clk/bcm/
H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
42 /* Clock field state tests */
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
61 return (u64)div->u.fixed; in scaled_div_min()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
89 return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width)); in divider()
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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
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/linux/drivers/clk/imx/
H A Dclk-gate2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Gated clock implementation
9 #include <linux/clk-provider.h>
19 * DOC: basic gateable clock which can gate and ungate its output
21 * Traits of this clock:
22 * prepare - clk_(un)prepare only ensures parent is (un)prepared
23 * enable - clk_enable and clk_disable are functional & control gating
24 * rate - inherits rate from parent. No clk_set_rate support
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/linux/drivers/clk/sunxi/
H A Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
21 * Traits of this clock:
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
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H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
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/linux/drivers/clk/qcom/
H A Dclk-cbf-8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
8 #include <linux/interconnect-clk.h>
9 #include <linux/interconnect-provider.h>
15 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-regmap.h"
112 regmap_read(clkr->regmap, mux->reg, &val); in clk_cbf_8996_mux_get_parent()
125 return regmap_update_bits(clkr->regmap, mux->reg, CBF_MUX_PARENT_MASK, val); in clk_cbf_8996_mux_set_parent()
133 if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) in clk_cbf_8996_mux_determine_rate()
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/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
199 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
207 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
208 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * common clock driver support for the MPC512x platform
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
69 /* data required for the OF clock provider registration */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
90 * those differences can get folded into this clock provider support
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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/linux/drivers/clk/microchip/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
39 /* Peripheral Bus Clock Reg Fields */
72 /* Clock Poll Timeout */
75 /* SoC specific clock needed during SPLL clock rate switch */
78 /* add instruction pipeline delay while CPU clock is in-transition. */
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
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/linux/drivers/iio/trigger/
H A Dstm32-timer-trigger.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/iio/timer/stm32-timer-trigger.h>
14 #include <linux/mfd/stm32-timers.h>
129 /* Period and prescaler values depends of clock rate */ in stm32_timer_start()
130 div = (unsigned long long)clk_get_rate(priv->clk); in stm32_timer_start()
140 while (div > priv->max_arr) { in stm32_timer_start()
148 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); in stm32_timer_start()
149 return -EINVAL; in stm32_timer_start()
153 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_start()
155 return -EBUSY; in stm32_timer_start()
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/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
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