Lines Matching +full:gated +full:- +full:fixed +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Gated clock implementation
9 #include <linux/clk-provider.h>
19 * DOC: basic gateable clock which can gate and ungate its output
21 * Traits of this clock:
22 * prepare - clk_(un)prepare only ensures parent is (un)prepared
23 * enable - clk_enable and clk_disable are functional & control gating
24 * rate - inherits rate from parent. No clk_set_rate support
25 * parent - fixed parent. No clk_set_parent support
46 reg = readl(gate->reg); in clk_gate2_do_shared_clks()
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
50 writel(reg, gate->reg); in clk_gate2_do_shared_clks()
58 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
65 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
75 spin_lock_irqsave(gate->lock, flags); in clk_gate2_disable()
77 if (gate->share_count) { in clk_gate2_disable()
78 if (WARN_ON(*gate->share_count == 0)) in clk_gate2_disable()
80 else if (--(*gate->share_count) > 0) in clk_gate2_disable()
86 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_disable()
106 spin_lock_irqsave(gate->lock, flags); in clk_gate2_is_enabled()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
109 gate->cgr_val, gate->cgr_mask); in clk_gate2_is_enabled()
111 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_is_enabled()
121 spin_lock_irqsave(gate->lock, flags); in clk_gate2_disable_unused()
123 if (!gate->share_count || *gate->share_count == 0) in clk_gate2_disable_unused()
126 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_disable_unused()
149 return ERR_PTR(-ENOMEM); in clk_hw_register_gate2()
152 gate->reg = reg; in clk_hw_register_gate2()
153 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
154 gate->cgr_val = cgr_val; in clk_hw_register_gate2()
155 gate->cgr_mask = cgr_mask; in clk_hw_register_gate2()
156 gate->flags = clk_gate2_flags; in clk_hw_register_gate2()
157 gate->lock = lock; in clk_hw_register_gate2()
158 gate->share_count = share_count; in clk_hw_register_gate2()
166 gate->hw.init = &init; in clk_hw_register_gate2()
167 hw = &gate->hw; in clk_hw_register_gate2()