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Searched +full:fsd +full:- +full:clk (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dtesla,fsd-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - linux-fsd@tesla.com
14 FSD clock controller consist of several clock management unit
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
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/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "tesla,fsd";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,s5p-mfc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Aakarsh Jain <aakarsh.jain@samsung.com>
20 - enum:
21 - samsung,exynos5433-mfc # Exynos5433
22 - samsung,mfc-v5 # Exynos4
23 - samsung,mfc-v6 # Exynos5
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/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
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/linux/drivers/clk/samsung/
H A Dclk-fsd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
5 * Copyright (c) 2017-2022 Tesla, Inc.
8 * Common Clock Framework support for FSD SoC.
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/fsd-clk.h>
20 #include "clk.h"
21 #include "clk-exynos-arm64.h"
322 CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
59 * Exynos ARMv7, Exynos ARMv8, Tesla FSD.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
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/linux/sound/soc/samsung/
H A Di2s.c1 // SPDX-License-Identifier: GPL-2.0
3 // ALSA SoC Audio Layer - Samsung I2S Controller driver
8 #include <dt-bindings/sound/samsung-i2s.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
21 #include <linux/platform_data/asoc-s3c.h>
26 #include "i2s-regs.h"
102 struct clk *clk; member
105 struct clk *op_clk;
123 struct clk *clk_table[3];
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/linux/drivers/spi/
H A Dspi-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
17 #include <linux/platform_data/spi-s3c64xx.h>
27 /* Registers and bit-fields */
112 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
114 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
115 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \
116 __ffs((sdd)->tx_fifomask))
117 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \
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/linux/drivers/ufs/host/
H A Dufs-exynos.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
14 #include <linux/clk.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
101 /* Multi-host registers */
210 if (ufs->sysreg) { in exynos_ufs_shareability()
211 return regmap_update_bits(ufs->sysreg, in exynos_ufs_shareability()
212 ufs->shareability_reg_offset, in exynos_ufs_shareability()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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