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/linux/drivers/cpufreq/
H A Dimx6q-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/nvmem-consumer.h>
83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
116 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it in imx6q_set_target()
117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it in imx6q_set_target()
118 * - Disable pll2_pfd2_396m_clk in imx6q_set_target()
169 /* PLL1 is only needed until after ARM-PODF is set. */ in imx6q_set_target()
194 policy->clk = clks[ARM].clk; in imx6q_cpufreq_init()
196 policy->suspend_freq = max_freq; in imx6q_cpufreq_init()
209 .name = "imx6q-cpufreq",
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H A Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
50 priv = policy->driver_data; in scmi_cpufreq_get_rate()
52 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
59 * perf_ops->freq_set is not a synchronous, the actual OPP change will
66 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
67 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target() local
69 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
75 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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/linux/net/ipv6/
H A Dip6_flowlabel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 /* FL hash table */
49 /* FL hash table lock: it protects only of GC */
57 DEFINE_STATIC_KEY_DEFERRED_FALSE(ipv6_flowlabel_exclusive, HZ);
63 fl = rcu_dereference(fl->next))
65 for (fl = rcu_dereference(fl->nex
376 fl_create(struct net * net,struct sock * sk,struct in6_flowlabel_req * freq,sockptr_t optval,int optlen,int * err_p) fl_create() argument
505 ipv6_flowlabel_opt_get(struct sock * sk,struct in6_flowlabel_req * freq,int flags) ipv6_flowlabel_opt_get() argument
545 ipv6_flowlabel_put(struct sock * sk,struct in6_flowlabel_req * freq) ipv6_flowlabel_put() argument
580 ipv6_flowlabel_renew(struct sock * sk,struct in6_flowlabel_req * freq) ipv6_flowlabel_renew() argument
612 ipv6_flowlabel_get(struct sock * sk,struct in6_flowlabel_req * freq,sockptr_t optval,int optlen) ipv6_flowlabel_get() argument
729 struct in6_flowlabel_req freq; ipv6_flowlabel_opt() local
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/linux/drivers/media/dvb-frontends/
H A Dstv0900_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
45 /* One point of the lookup table */
51 /* Lookup table definition */
53 s32 size;/* Size of the lookup table */
54 struct stv000_lookpoint table[STV0900_MAXLOOKUPSIZE];/* Lookup table */ member
126 STV0900_BLIND_SEARCH,/* offset freq and SR are Unknown */
128 STV0900_WARM_START/* offset freq and SR are known */
226 u32 dmd_ref_clk;/* Reference,Input clock for the demod in Hz */
255 u32 search_range;/* Range of the search (in Hz) */
295 s32 freq[2]; member
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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H A Dsm6350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
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H A Dsm6375.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
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H A Dsc8180x.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sc8180x-camcc.h>
13 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
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H A Dtalos.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,qcs615-camcc.h>
8 #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
9 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
10 #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
11 #include <dt-bindings/clock/qcom,qcs615-videocc.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
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/linux/arch/arm/include/asm/
H A Ddelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1995-2004 Russell King
5 * Delay routines, using a pre-computed "loops_per_second" value.
11 #include <asm/param.h> /* HZ */
20 * jiffies_per_sec = HZ
23 * Therefore the constant part is HZ / 1000000 which is a small
32 * UDELAY_MULT = 2^31 * HZ / 1000000
33 * = (2^31 / 1000000) * HZ
34 * = 2147.483648 * HZ
35 * = 2147 * HZ + 483648 * HZ / 1000000
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/linux/arch/m68k/mac/
H A Dmacboing.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mac bong noise generator. Note - we ought to put a boingy noise
6 * ----------------------------------------------------------------------
10 * Juergen Mellinger (juergen.mellinger@t-online.de)
23 * dumb triangular wave table
37 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
71 switch ( macintosh_config->ident ) in mac_init_asc()
99 * current location of the Apple Sound Chip--ASC--in other Macs.) The in mac_init_asc()
104 * Macintosh models have 16-bit audio input and output capability in mac_init_asc()
105 * because of the AT&T DSP3210 hardware circuitry and the 16-bit Singer in mac_init_asc()
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c1 // SPDX-License-Identifier: GPL-2.0+
59 {148500, 1920, 1080, 60, 11, 49, 3}, /* 1920x1080@60Hz */
60 {141750, 1920, 1080, 60, 11, 78, 5}, /* 1920x1080@60Hz */
61 /* 1920x1080@50Hz */
62 {174500, 1920, 1080, 75, 17, 89, 3}, /* 1920x1080@75Hz */
63 {181250, 2560, 1080, 75, 8, 58, 4}, /* 2560x1080@75Hz */
64 {297000, 2560, 1080, 30, 8, 95, 4}, /* 3840x2160@30Hz */
65 {301992, 1920, 1080, 100, 10, 151, 5}, /* 1920x1080@100Hz */
432 unsigned int freq; lsdc_pixpll_get_freq() local
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/linux/drivers/net/wireless/ath/ath5k/
H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
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/linux/Documentation/power/
H A Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
39 We can represent these as three OPPs as the following {Hz, uV} tuples:
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
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/linux/Documentation/devicetree/bindings/ufs/
H A Damd,versal2-ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 - $ref: ufs-common.yaml
17 const: amd,versal2-ufs
25 clock-names:
27 - const: core
29 power-domains:
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H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
24 - $ref: ufs-common.yaml
29 - enum:
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H A Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
25 clock-names:
27 - const: fck
28 - const: ref_clk
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H A Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
24 - $ref: ufs-common.yaml
29 - items:
30 - const: hisilicon,hi3660-ufs
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H A Dmediatek,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Wang <peter.wang@mediatek.com>
11 - Chaotian Jing <chaotian.jing@mediatek.com>
16 - mediatek,mt8183-ufshci
17 - mediatek,mt8192-ufshci
18 - mediatek,mt8195-ufshci
24 clock-names:
34 vcc-supply: true
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/linux/sound/soc/codecs/
H A Dpeb2466.c1 // SPDX-License-Identifier: GPL-2.0
3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver
25 u8 (*table)[4]; member
42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
136 .tx_buf = &peb2466->spi_tx_buf, in peb2466_write_byte()
140 peb2466->spi_tx_bu in peb2466_write_byte()
1191 u8 (*table)[4]; peb2466_fw_parse_axtable() local
1295 u8 (*table)[4]; peb2466_fw_parse_artable() local
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/linux/drivers/devfreq/
H A Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
50 * +----------+ | | |
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