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/linux/Documentation/devicetree/bindings/ufs/
H A Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
[all …]
H A Dmediatek,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanley Chu <stanley.chu@mediatek.com>
13 - $ref: ufs-common.yaml
18 - mediatek,mt8183-ufshci
19 - mediatek,mt8192-ufshci
24 clock-names:
26 - const: ufs
34 vcc-supply: true
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H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
24 - $ref: ufs-common.yaml
29 - enum:
[all …]
H A Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
25 clock-names:
27 - const: fck
28 - const: ref_clk
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/linux/drivers/ufs/host/
H A Dufshcd-pltfrm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011-2013 Samsung India Software Operations
19 #include "ufshcd-pltfrm.h"
29 struct device *dev = hba->dev; in ufshcd_parse_clock_info()
30 struct device_node *np = dev->of_node; in ufshcd_parse_clock_info()
39 cnt = of_property_count_strings(np, "clock-names"); in ufshcd_parse_clock_info()
40 if (!cnt || (cnt == -EINVAL)) { in ufshcd_parse_clock_info()
52 sz = of_property_count_u32_elems(np, "freq-table-hz"); in ufshcd_parse_clock_info()
54 dev_info(dev, "freq-table-hz property not specified\n"); in ufshcd_parse_clock_info()
59 dev_err(dev, "%s len mismatch\n", "freq-table-hz"); in ufshcd_parse_clock_info()
[all …]
/linux/drivers/opp/
H A Dof.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
34 /* "operating-points-v2" can be an array for power domain providers */ in _opp_of_get_opp_desc_node()
35 return of_parse_phandle(np, "operating-points-v2", index); in _opp_of_get_opp_desc_node()
41 return _opp_of_get_opp_desc_node(dev->of_node, 0); in dev_pm_opp_of_get_opp_desc_node()
50 np = _opp_of_get_opp_desc_node(dev->of_node, index); in _managed_opp()
55 if (opp_table->np == np) { in _managed_opp()
57 * Multiple devices can point to the same OPP table and in _managed_opp()
58 * so will have same node-pointer, np. in _managed_opp()
61 * OPP table contains a "opp-shared" property. in _managed_opp()
[all …]
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
26 * The root of the list of all opp-tables. All opp_table structures branch off
44 guard(mutex)(&opp_table->lock); in _find_opp_dev()
46 list_for_each_entry(opp_dev, &opp_table->dev_list, node) in _find_opp_dev()
47 if (opp_dev->dev == dev) in _find_opp_dev()
62 return ERR_PTR(-ENODEV); in _find_opp_table_unlocked()
66 * _find_opp_table() - find opp_table struct using device pointer
67 * @dev: device pointer used to lookup OPP table
69 * Search OPP table for one containing matching device.
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/linux/drivers/cpufreq/
H A Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
49 priv = policy->driver_data; in scmi_cpufreq_get_rate()
51 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
58 * perf_ops->freq_set is not a synchronous, the actual OPP change will
65 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
66 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target() local
68 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
74 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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/linux/net/ipv6/
H A Dip6_flowlabel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 /* FL hash table */
49 /* FL hash table lock: it protects only of GC */
57 DEFINE_STATIC_KEY_DEFERRED_FALSE(ipv6_flowlabel_exclusive, HZ);
63 fl = rcu_dereference(fl->next))
65 for (fl = rcu_dereference(fl->next); \
67 fl = rcu_dereference(fl->next))
70 for (sfl = rcu_dereference(np->ipv6_fl_list); \
72 sfl = rcu_dereference(sfl->next))
79 if (fl->label == label && net_eq(fl->fl_net, net)) in __fl_lookup()
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/linux/drivers/media/dvb-frontends/
H A Dstv0900_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
45 /* One point of the lookup table */
51 /* Lookup table definition */
53 s32 size;/* Size of the lookup table */
54 struct stv000_lookpoint table[STV0900_MAXLOOKUPSIZE];/* Lookup table */ member
126 STV0900_BLIND_SEARCH,/* offset freq and SR are Unknown */
128 STV0900_WARM_START/* offset freq and SR are known */
226 u32 dmd_ref_clk;/* Reference,Input clock for the demod in Hz */
255 u32 search_range;/* Range of the search (in Hz) */
295 s32 freq[2]; member
/linux/drivers/media/i2c/
H A Dsaa7115.c1 // SPDX-License-Identifier: GPL-2.0+
2 // saa711x - Philips SAA711x video decoder driver
23 // Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-mc.h>
49 MODULE_PARM_DESC(debug, "Debug level (0-1)");
104 return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd; in to_sd()
107 /* ----------------------------------------------------------------------- */
164 filled with 0 - seems better not to touch on they */ in saa711x_writeregs()
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/linux/arch/m68k/mac/
H A Dmacboing.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mac bong noise generator. Note - we ought to put a boingy noise
6 * ----------------------------------------------------------------------
10 * Juergen Mellinger (juergen.mellinger@t-online.de)
23 * dumb triangular wave table
37 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
71 switch ( macintosh_config->ident ) in mac_init_asc()
99 * current location of the Apple Sound Chip--ASC--in other Macs.) The in mac_init_asc()
104 * Macintosh models have 16-bit audio input and output capability in mac_init_asc()
105 * because of the AT&T DSP3210 hardware circuitry and the 16-bit Singer in mac_init_asc()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
[all …]
H A Dsm6350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
[all …]
H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
[all …]
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
[all …]
H A Dsc8180x.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/interconnect/qcom,icc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/linux/arch/arm/include/asm/
H A Ddelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1995-2004 Russell King
5 * Delay routines, using a pre-computed "loops_per_second" value.
11 #include <asm/param.h> /* HZ */
20 * jiffies_per_sec = HZ
23 * Therefore the constant part is HZ / 1000000 which is a small
32 * UDELAY_MULT = 2^31 * HZ / 1000000
33 * = (2^31 / 1000000) * HZ
34 * = 2147.483648 * HZ
35 * = 2147 * HZ + 483648 * HZ / 1000000
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
[all …]
/linux/include/linux/
H A Dpm_opp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
32 * struct dev_pm_opp_supply - Power supply voltage/current values
58 * struct dev_pm_opp_config - Device OPP configuration values
87 * struct dev_pm_opp_data - The data to use to initialize an OPP.
91 * @freq: The clock rate in Hz for the OPP.
97 unsigned long freq; member
131 unsigned long freq,
135 dev_pm_opp_find_freq_exact_indexed(struct device *dev, unsigned long freq,
139 unsigned long *freq);
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c1 // SPDX-License-Identifier: GPL-2.0+
58 {148500, 1920, 1080, 60, 11, 49, 3}, /* 1920x1080@60Hz */
59 {141750, 1920, 1080, 60, 11, 78, 5}, /* 1920x1080@60Hz */
60 /* 1920x1080@50Hz */
61 {174500, 1920, 1080, 75, 17, 89, 3}, /* 1920x1080@75Hz */
62 {181250, 2560, 1080, 75, 8, 58, 4}, /* 2560x1080@75Hz */
63 {297000, 2560, 1080, 30, 8, 95, 4}, /* 3840x2160@30Hz */
64 {301992, 1920, 1080, 100, 10, 151, 5}, /* 1920x1080@100Hz */
65 {146250, 1680, 1050, 60, 16, 117, 5}, /* 1680x1050@60Hz */
66 {135000, 1280, 1024, 75, 10, 54, 4}, /* 1280x1024@75Hz */
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
[all …]
/linux/Documentation/power/
H A Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
39 We can represent these as three OPPs as the following {Hz, uV} tuples:
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
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/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
77 * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
90 unsigned long freq; member
[all …]
/linux/sound/soc/codecs/
H A Dpeb2466.c1 // SPDX-License-Identifier: GPL-2.0
3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver
25 u8 (*table)[4]; member
42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
136 .tx_buf = &peb2466->spi_tx_buf, in peb2466_write_byte()
140 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; in peb2466_write_byte()
141 peb2466->spi_tx_buf[1] = val; in peb2466_write_byte()
143 dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n", in peb2466_write_byte()
144 peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]); in peb2466_write_byte()
[all …]

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